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t48c893 t48c893 rev. a4, 22-jan-02 1 (82) flash version for m44c090/890 and m44c092/892 the t48c893 is the multiple times programmable (mtp) version for the marc4 rom types m44c090/890, m44c092/892. the mtp is designed with eeprom cells so it can be programmed several times. to of fer full compati- bility with each rom version, the i/o configuration is stored into a separate internal eeprom block during programming.the configuration is download to the i/os with every power-on reset.. features / benefits 4-kbyte eeprom program memory eeprom programmable options read protection for the eeprom program memory 16 bidirectional i/os up to 7 external / internal interrupt sources 8 hardware and software interrupt priorities multifunction timer/counter with prescaler/interval timer programmable system-clock with prescaler and five different clock sources wide supply voltage range (1.8 to 6.5 v) very low sleep current (< 1 a) 2 512 bit eeprom data memory 256 4 bit ram data memory synchronous serial interface (2-wire, i 2 c, 3-wire) watchdog, por and brown-out function voltage monitoring incl. lo_bat detect multi-chip link for u3280m voltage monitor external input marc4 utcm osc1 osc2 i/o bus eeprom ram 4-bit cpu core 256 x 4 bit v dd v ss data direction + alternate function data direction + interrupt control port 4 port 5 data dir. + alt. function port 6 timer 3 brown-out protect. reset clock management timer 1 watchdog timer timer 2 serial interface port 1 port 2 data direction t2o sd sc t3o t3i bp10 bp13 bp20/nte bp21 bp22 bp23 bp40 int3 sc bp41 vmi t2i bp42 t2o bp43 int3 sd bp50 int6 bp51 int6 bp52 int1 bp53 int1 bp60 t3o bp63 t3i rc oscillators crystal oscillators 4 k x 8 bit vmi with modulator ssi external clock input interval- and 8/12-bit timer 8-bit timer / counter with modulator and demodulator t2i 4 k x 8 bit eeprom 2 32 16 bit figure 1. block diagram t48c893
t48c893 rev. a4, 22-jan-02 2 (82) t48c893 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 16 v dd bp40/int3/sc bp53/int1 bp52/int1 bp51/int6 bp50/int6 osc1 osc2 bp60/t3o bp10 v ss bp43/int3/sd bp42/t2o bp41/vmi/t2i bp23 bp22 bp21 bp20/nte bp63/t3i bp13 figure 2. pinning sso20 package table 1 pin description name type function alternate function pin-no. reset state v dd supply voltage ??? 1 na v ss circuit ground ??? 20 na bp10 i/o bidirectional i/o line of port 1.0 ??? 10 input bp13 i/o bidirectional i/o line of port 1.3 ??? 11 input bp20 i/o bidirectional i/o line of port 2.0 nte?test mode enable 13 input bp21 i/o bidirectional i/o line of port 2.1 ??? 14 input bp22 i/o bidirectional i/o line of port 2.2 ??? 15 input bp23 i/o bidirectional i/o line of port 2.3 ??? 16 input bp40 i/o bidirectional i/o line of port 4.0 sc-serial clock or int3 external interrupt input 2 input bp41 i/o bidirectional i/o line of port 4.1 vmi voltage monitor input or t2i external clock input timer 2 17 input bp42 i/o bidirectional i/o line of port 4.2 t2o timer 2 output 18 input bp43 i/o bidirectional i/o line of port 4.3 sd serial data i/o or int3 exter- nal interrupt input 19 input bp50 i/o bidirectional i/o line of port 5.0 int6 external interrupt input 6 input bp51 i/o bidirectional i/o line of port 5.1 int6 external interrupt input 5 input bp52 i/o bidirectional i/o line of port 5.2 int1 external interrupt input 4 input bp53 i/o bidirectional i/o line of port 5.3 int1 external interrupt input 3 input bp60 i/o bidirectional i/o line of port 6.0 t3o timer 3 output 9 input bp63 i/o bidirectional i/o line of port 6.3 t3i timer 3 input 12 input osc1 i oscillator input 4-mhz crystal input or 32-khz crystal input or external clock in- put or external trimming resistor input 7 input osc2 o oscillator output 4-mhz crystal output or 32-khz crystal output or external clock input 8 input
t48c893 t48c893 rev. a4, 22-jan-02 3 (82) table of contents 1 introduction 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 differences between t48c893 and m44cx90/x92 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 program memory 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 configuration memory 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 data memory 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 reset function 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 marc4 architecture 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 general description 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 components of marc4 core 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 program memory 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 ram 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 registers 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 alu 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 i/o bus 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 instruction set 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 interrupt structure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software interrupts 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hardware interrupts 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 master reset 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 power-on reset and brown-out detection 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 watchdog reset 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 external clock supervisor 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 voltage monitor 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 voltage monitor control / status register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 clock generation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 clock module 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 oscillator circuits and external clock input stage 18 . . . . . . . . . . . . . . . . . . . . . . . . rc-oscillator 1 fully integrated 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external input clock 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rc-oscillator 2 with external trimming resistor 18 . . . . . . . . . . . . . . . . . . . . . . . . . 4-mhz oscillator 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-khz oscillator 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 clock management 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock management register (cm) 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system configuration register (sc) 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 power-down modes 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 peripheral modules 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 addressing peripherals 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 bidirectional ports 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 bidirectional port 1 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 bidirectional port 2 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . port 2 data register (p2dat) 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . port 2 control register (p2cr) 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
t48c893 rev. a4, 22-jan-02 4 (82) table of contents (continued) 4.2.3 bidirectional port 5 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 bidirectional port 4 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 bidirectional port 6 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 universal timer/counter / communication module (utcm) 29 . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 timer 1 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 1 control register 1 (t1c1) 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 1 control register 2 (t1c2) 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog control register (wdc) 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 timer 2 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 modes 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 output modes 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 output signals 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 registers 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 control register (t2c) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 mode register 1 (t2m1) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 mode register 2 (t2m2) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 compare and compare mode registers 41 . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 compare mode register (t2cm) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 compare register 1 (t2co1) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 2 compare register 2 (t2co2) byte write 41 . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 timer 3 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer / counter modes 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 modulator / demodulator modes 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 modulator for carrier frequency burst modulation 48 . . . . . . . . . . . . . . . . timer 3 demodulator for biphase, manchester and pulse-width-modulated signals 48 timer 3 registers 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 mode register (t3m) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 control register 1 (t3c) write 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 status register 1 (t3st) read 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 clock select register (t3cs) 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 compare- and compare mode register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 compare mode register 1 (t3cm1) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 compare mode register 2 (t3cm2) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 compare register 1 (t3co1) byte write 52 . . . . . . . . . . . . . . . . . . . . . . . . timer 3 compare register 2 (t3co2) byte write 52 . . . . . . . . . . . . . . . . . . . . . . . . timer 3 capture register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 3 capture register (t3cp) byte read 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 synchronous serial interface (ssi) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ssi peripheral configuration 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general ssi operation 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bit synchronous mode 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-bit shift mode (i2c compatible) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
t48c893 t48c893 rev. a4, 22-jan-02 5 (82) table of contents (continued) 8-bit pseudo i2c mode 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i2c bus protocol 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ssi interrupt 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . modulation and demodulation 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internal 2-wire multi-chip link 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial interface registers 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial interface control register 1 (sic1) 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial interface control register 2 (sic2) 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial interface status and control register (sisc) 61 . . . . . . . . . . . . . . . . . . . . . . . serial transmit buffer (stb) ? byte write 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial receive buffer (srb) ? byte read 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 combination modes 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . combination mode timer 2 and ssi 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . combination mode timer 3 and ssi 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . combination mode timer 2 and timer 3 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . combination mode timer 2, timer 3 and ssi 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 data eeprom 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 serial interface 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial protocol 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 eeprom 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eeprom ? operating modes 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . write operations 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . read operations 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . initialization the serial interface to the eeprom 75 . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical characteristics 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 absolute maximum ratings 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 dc operating characteristics 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 ac characteristics 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 package information 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 selectable options 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
t48c893 rev. a4, 22-jan-02 6 (82) ordering information extended type number package remarks t48c893 ? tk sso20 tube t48c893 ? tkq sso20 taped and reeled 1 introduction the t48c893 is a member of atmels family of 4-bit single-chip microcontrollers. instead of rom it contains eeprom, ram, parallel i/o ports, two 8-bit program- mable multifunction timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated rc-, 32-khz crystal- and 4-mhz crystal-oscillators. 2 differences between t48c893 and m44cx90/x92 2.1 program memory the program memory of the mtp devices is realized as an eeprom. the memory size for user programs is 4096 bytes. it is programmed as 258 16 byte blocks of data. the implemented lock-bit function is user select- able and protects the device from unauthorized read-out of the program memory. 2.2 configuration memory an additional area of 32 bytes of the eeprom is used to store information about the hardware configuration. all the options that are selectable for the rom versions are available to the user. this includes not only the different port options but also the possibilities to select different ca- pacitors for osc1 and osc2, the option to enable or disable the hardlock for the watchdog, the option to select osc2 instead of osc1 as external clock input and the op- tion to enable the external clock monitor as a reset source. 2.3 data memory the t48c893 contains an internal data eeprom that is organized as two pages of 32 16 bit. to be compatible with the rom parts, the page used has to be defined within the application software by writing the i 2 c-com- mand ? 09h ? to the eeprom. this command has no effect for the m44cx90/x92 if it is left inside the hex-file for the rom version. also for compatibility reasons the access to the eeprom is handled via the mcl (serial in- terface) as in the corresponding rom parts. 2.4 reset function during each reset (power-on or brown-out) the i/o-con- figuration is deleted and reloaded with the data from the configuration memory. this leads to a slightly different behavior compared to the rom versions. both devices switch their i/os to input during reset but the rom part has the mask selected pull-up or pull-down resistors ac- tive while the mtp has them removed until the download is finished.
t48c893 t48c893 rev. a4, 22-jan-02 7 (82) 3 marc4 architecture 3.1 general description the marc4 microcontroller consists of an advanced stack-based, 4-bit cpu core and on-chip peripherals. the cpu is based on the harvard architecture with physically separate program memory (rom) and data memory (ram). three independent buses, the instruction bus, the memory bus and the i/o bus, are used for parallel communication between rom, ram and peripherals. this enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. the extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. the m arc4 is designed for the high-level programming language qforth. the core includes both, an expression and a return stack. this architecture enables high-level language programming without any loss of efficiency or code density. ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ?? ?? ?? instruction decoder ccr tos alu ram pc rp sp x y program 256 x 4-bit marc4 core clock reset sleep memory bus i/o bus instruction bus reset system clock interrupt controller on ? chip peripheral modules 94 8973 memory figure 3. marc4 core
t48c893 rev. a4, 22-jan-02 8 (82) 3.2 components of marc4 core eeprom (4 k x 8 bit) zero page fffh 7ffh 1ffh 000h 1f0h 1f8h 010h 018h 000h 008h 020h 1e8h 1e0h scall addresses 140h 180h 040h 0c0h 008h $autosleep $reset int0 int1 int2 int3 int4 int5 int6 int7 1e0h 1c0h 100h 080h zero page 000h figure 4. rom map of t48c893 the core contains rom, ram, alu, program counter, ram address registers, instruction decoder and interrupt controller. the following sections describe each functional block in more detail: 3.2.1 program memory the program memory (eeprom) is programmed with the application program. the eeprom is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 kbytes. the lowest user program-memory address segment is taken up by a 512 byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (scall). the corresponding memory map is shown in figure 4. look-up tables of constants can also be held in rom and are accessed via the marc4 ? s built-in table instruction. 3.2.2 ram the t48c893 contains 256 x 4-bit wide static random access memory (ram). it is used for the expression stack, the return stack and data memory for variables and arrays. the ram is addressed by any of the four 8-bit wide ram address registers sp, rp, x and y. expression stack the 4-bit wide expression stack is addressed with the expression stack pointer (sp). all arithmetic, i/o and memory reference operations take their operands from, and return their results to the expression stack. the marc4 performs the operations with the top of stack items (tos and tos ? 1). the tos register contains the top element of the expression stack and works in the same way as an accumulator. this stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. return stack the 12-bit wide return stack is addressed by the return stack pointer (rp). it is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. the return stack can also be used as a temporary storage area. the marc4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. the two stacks within the ram have a user definable location and maximum depth.
t48c893 t48c893 rev. a4, 22-jan-02 9 (82) ??? ??? ???? ???? ??????? ??????? ????? ????? ????? ????? ????? ????? ????? ??? ??? ram fch 00h autosleep ffh 03h 04h x y sp rp tos?1 expression stack return stack global variables ram address register: 07h (256 x 4-bit) global variables 4-bit tos tos ? 1 tos ? 2 30 sp expression stack return stack ????? ????? 0 11 12-bit rp v 94 8975 figure 5. ram map 3.2.3 registers the marc4 controller has seven programmable registers and one condition code register. they are shown in the following programming model. program counter (pc) the program counter (pc) is a 12-bit register which contains the address of the next instruction to be fetched from the rom. instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. for linear code (no calls or branches) the program counter is incremented with every instruction cycle. if a branch-, call-, return-instruction or an interrupt is executed, the program counter is loaded with a new address. the program counter is also used with the table instruction to fetch 8-bit wide rom constants. tos ccr 0 3 0 3 0 7 0 7 7 0 11 rp sp x y pc ?? b i program counter return stack pointer expression stack pointer ram addr ess r egister (x) ram addr ess r egister (y) top of stack register condition code register carry / borrow branch interrupt enable reserved 0 7 c 0 0 0 figure 6. programming model
t48c893 rev. a4, 22-jan-02 10 (82) ram address registers the ram is addressed with the four 8-bit wide ram address registers: sp, rp, x and y. these registers allow access to any of the 256 ram nibbles. expression stack pointer (sp) the stack pointer (sp) contains the address of the next-to- top 4-bit item (tos ? 1) of the expression stack. the pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. every post-decrement operation moves the item (tos ? 1) to the tos register before the sp is decremented. after a reset the stack pointer has to be initialized with ? >sp s0 ? to allocate the start address of the expression stack area. return stack pointer (rp) the return stack pointer points to the top element of the 12-bit wide return stack. the pointer automatically pre- increments if an element is moved onto the stack, or it post-decrements if an element is removed from the stack. the return stack pointer increments and decrements in steps of 4. this means that every time a 12-bit element is stacked, a 4-bit ram location is left unwritten. this location is used by the qforth compiler to allocate 4-bit variables. after a reset the return stack pointer has to be initialized via ? >rp fch ? . ram address registers (x and y) the x and y registers are used to address any 4-bit item in the ram. a fetch operation moves the addressed nibble onto the tos. a store operation moves the tos to the addressed ram location. by using either the pre ? increment or post ? decrement addressing mode arrays in the ram can be compared, filled or moved. top of stack (tos) the top of stack register is the accumulator of the marc4. all arithmetic/logic, memory reference and i/o operations use this register. the tos register receives data from the alu, rom, ram or i/o bus. condition code register (ccr) the 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. these bits indicate the current state of the cpu. the ccr flags are set or reset by alu operations. the instructions set_bcf, tog_bf, ccr! and di allow direct manipulation of the condition code register. carry/borrow (c) the carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit ( alu ) occurred during the last arithmetic operation. during shift and rotate operations, this bit is used as a fifth bit. boolean operations have no affect on the c-flag. branch (b) the branch flag controls the conditional program branching. should the branch flag have been set by a previous instruction a conditional branch will cause a jump. this flag is affected by arithmetic, logic, shift, and rotate operations. interrupt enable (i) the interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. after a reset or on executing the di instruction, the interrupt enable flag is reset thus disabling all interrupts. the core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an ei, rti or sleep instruction.
t48c893 t48c893 rev. a4, 22-jan-02 11 (82) 3.2.4 alu ?? ?? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ????? ????? ????? ????? ????? ????? ????? ????? ????? ???????? ???? ???? tos ? 1 ccr ram ???? ???? tos ? 2 sp tos ? 3 ????? ????? ????? ??????? ??????? ??????? tos alu tos ? 4 94 8977 figure 7. alu zero-address operations the 4-bit alu performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (tos and tos ? 1) and returns the result to the tos. the alu operations affect the carry/borrow and branch flag in the condition code register (ccr). 3.2.5 i/o bus the i/o ports and the registers of the peripheral modules are i/o mapped. all communication between the core and the on-chip peripherals takes place via the i/o bus and the associated i/o control. with the marc4 in and out instructions the i/o bus allows a direct read or write access to one of the 16 primary i/o addresses. more about the i/o access to the on-chip peripherals is described in the section ? peripheral modules ? . the i/o bus is internal and is not accessible by the customer on the final micro- controller device, but it is used as the interface for the marc4 emulation (see also the section ? emulation ? ). 3.2.6 instruction set the marc4 instruction set is optimized for the high level programming language qforth. many marc4 instructions are qforth words. this enables the compiler to generate a fast and compact program code. the cpu has an instruction pipeline allowing the controller to prefetch an instruction from program memory at the same time as the present instruction is being executed. the marc4 is a zero address machine, the instructions containing only the operation to be performed and no source or destination address fields. the operations are implicitly performed on the data placed on the stack. there are one and two byte instructions which are executed within 1 to 4 machine cycles. a marc4 machine cycle is made up of two system clock cycles (syscl). most of the instructions are only one byte long and are executed in a single machine cycle. for more information refer to the ? marc4 programmer ? s guide ? . 3.2.7 interrupt structure the marc4 can handle interrupts with eight different priority levels. they can be generated from the internal and external interrupt sources or by a software interrupt from the cpu itself. each interrupt level has a hard-wired priority and an associated vector for the service routine in the program memory (see table 2). the programmer can postpone the processing of interrupts by resetting the interrupt enable flag (i) in the ccr. an interrupt occurrence will still be registered, but the interrupt routine only started after the i flag is set. all interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module. (see section ? peripheral modules ? ).
t48c893 rev. a4, 22-jan-02 12 (82) 7 6 5 4 3 2 1 0 priority level int5 active int7 active ??????? ??????? int2 pending swi0 int2 active ??????? ??????? int0 pending int0 active int2 rti rti int5 int3 active int3 rti rti rti int7 time main / autosleep main / autosleep 94 8978 figure 8. interrupt handling interrupt processing for processing the eight interrupt levels, the marc4 includes an interrupt controller with two 8-bit wide ? interrupt pending ? and ? interrupt active ? registers. the interrupt controller samples all interrupt requests during every non-i/o instruction cycle and latches these in the interrupt pending register. if no higher priority interrupt is present in the interrupt active register, it signals the cpu to interrupt the current program execution. if the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. during this cycle a short call (scall) instruction to the service routine is executed and the current pc is saved on the return stack. an interrupt service routine is completed with the rti instruction. this instruction sets the interrupt enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. when the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. the execution of the interrupt is delayed until the interrupt enable flag is set again. note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). it should also be noted that automatic stacking of the rbr is not carried out by the hardware and so if rom banking is used, the rbr must be stacked on the expression stack by the application program and restored before the rti. after a master reset (power-on, brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are all reset. interrupt latency the interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. in marc4 this is extremely short (taking between 3 to 5 machine cycles depending on the state of the core).
t48c893 t48c893 rev. a4, 22-jan-02 13 (82) table 2 interrupt priority table interrupt priority rom address interrupt opcode function int0 lowest 040h c8h (scall 040h) software interrupt (swi0) int1 | 080h d0h (scall 080h) external hardware interrupt, any edge at bp52 or bp53 int2 | 0c0h d8h (scall 0c0h) timer 1 interrupt int3 | 100h e8h (scall 100h) ssi interrupt or external hardware interrupt at bp40 or bp43 int4 | 140h e8h (scall 140h) timer 2 interrupt int5 | 180h f0h (scall 180h) timer 3 interrupt int6 1c0h f8h (scall 1c0h) external hardware interrupt, at any edge at bp50 or bp51 int7 highest 1e0h fch (scall 1e0h) voltage monitor (vm) interrupt table 3 hardware interrupts interrupt interrupt mask interrupt source register bit int1 p5cr p52m1, p52m2 p53m1, p53m2 any edge at bp52 any edge at bp53 int2 t1m t1im timer 1 int3 sisc sim ssi buffer full / empty or bp40/bp43 interrupt int4 t2cm t2im timer 2 compare match / overflow int5 t3cm1 t3cm2 t3c t3im1 t3im2 t3eim timer 3 compare register 1 match timer 3 compare register 2 match timer 3 edge event occurs (t3i) int6 p5cr p50m1, p50m2 p51m1, p51m2 any edge at bp50, any edge at bp51 int7 vcm vim external / internal voltage monitoring software interrupts the programmer can generate interrupts by using the software interrupt instruction (swi) which is supported in qforth by predefined macros named swi0...swi7. the software triggered interrupt operates exactly like any hardware triggered interrupt. the swi instruction takes the top two elements from the expression stack and writes the corresponding bits via the i/o bus to the interrupt pending register. therefore, by using the swi instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution. hardware interrupts in the t48c893, there are eleven hardware interrupt sources with seven different levels. each source can be masked individually by mask bits in the corresponding control registers. an overview of the possible hardware configurations is shown in table 4. 3.3 master reset the master reset forces the cpu into a well-defined condition. it is unmaskable and is activated independent of the current program state. it can be triggered by either initial supply power-up, a short collapse of the power sup- ply, brown-out detection circuitry, watchdog time-out, or an external input clock supervisor stage (see figure 9). a master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. during the power-on reset phase the i/o bus con- trol signals are set to ? reset mode ? thereby initializing all on-chip peripherals. all bidirectional ports are set to input mode. attention: during any reset phase, the bp20/nte input is driven towards v dd by a strong pull-up transistor. releasing the reset results in a short call instruction (opcode c1h) to the eeprom address 008h. this acti- vates the initialization routine $reset which in turn has to initialize all necessary ram variables, stack pointers and peripheral configuration registers (see table 7).
t48c893 rev. a4, 22-jan-02 14 (82) reset timer v dd cl power ? on reset internal reset res cl=syscl/4 v dd v ss brown ? out detection v dd v ss watch ? dog cwd res ext. clock supervisor exin pull-up nrst 13752 figure 9. reset configuration 3.3.1 power-on reset and brown-out detection the t48c893 has a fully integrated power-on reset and brown-out detection circuitry. for reset generation no ex- ternal components are needed . these circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. a reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power down mode is activated (the core is in sleep mode and the peripheral clock is stopped). in this power-down mode the brown- out detection is disabled. two values for the brown-out voltage threshold are programmable via the bot-bit in the sc-register. v dd cpu reset t bot = ? 1 ? 2.0 v 1.7 v cpu reset bot = ? 0 ? t d t d t d = 1.5 ms (typically) t d 13753 bot = 1, low brown-out voltage threshold. (1.7 v) is reset value. bot = 0, high brown-out voltage threshold (2.0 v). figure 10. brown-out detection
t48c893 t48c893 rev. a4, 22-jan-02 15 (82) a power-on reset pulse is generated by a v dd rise across the default bot voltage level (1.7 v). a brown-out reset pulse is generated when v dd falls below the brown-out voltage threshold. two values for the brown-out voltage threshold are programmable via the bot-bit in the sc-register. when the controller runs in the upper supply voltage range with a high system clock frequency, the high threshold must be used. when it runs with a lower system clock frequency, the low threshold and a wider supply voltage range may be chosen. for further details, see the electrical specification and the sc-register description for bot programming. 3.3.2 watchdog reset the watchdog ? s function can be enabled at the wdc-reg- ister and triggers a reset with every watchdog counter overflow. to supress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog register address (cwd). the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. 3.3.3 external clock supervisor the external input clock supervisor function can be enabled if the external input clock is selected within the cm- and sc-registers of the clock module. the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. 3.4 voltage monitor the voltage monitor consists of a comparator with internal voltage reference. it is used to supervise the supply voltage or an external voltage at the vmi-pin. the comparator for the supply voltage has three internal programmable thresholds one lower threshold (2.2 v), one middle threshold (2.6 v). and one higher threshold (3.0 v). for external voltages at the vmi-pin, the comparator threshold is set to v bg = 1.3 v. the vms-bit indicates if the supervised voltage is below (vms = 0) or above (vms = 1) this threshold. an interrupt can be generated when the vms-bit is set or reset to detect a rising or falling slope. a voltage monitor interrupt (int7) is enabled when the interrupt mask bit (vim) is reset in the vmc-register. v dd vm2 voltage monitor vm1 vm0 vim vms ? ? res out in bp41/ vmi int7 vmc : vmst : 13754 figure 11. voltage monitor
t48c893 rev. a4, 22-jan-02 16 (82) 3.4.1 voltage monitor control / status register primary register address: ? f ? hex bit 3 bit 2 bit 1 bit 0 vmc: write vm2 vm1 vm0 vim reset value: 1111b vmst: read ??? ??? reserved vms reset value: xx11b vm2: v oltage monitor m ode bit 2 vm1: v oltage monitor m ode bit 1 vm0: v oltage monitor m ode bit 0 vm2 vm1 vm0 function 1 1 1 disable voltage monitor 1 1 0 external (vim-input), internal reference threshold (1.3 v), interrupt with negative slope 1 0 1 not allowed 1 0 0 external (vmi-input), internal reference threshold (1.3 v), interrupt with positive slope 0 1 1 internal (supply voltage), high threshold (3.0 v), interrupt with negative slope 0 1 0 internal (supply voltage), middle threshold (2.6 v), interrupt with negative slope 0 0 1 internal (supply voltage), low threshold (2.2 v), interrupt with negative slope 0 0 0 not allowed vim v oltage i nterrupt m ask bit vim = 0, voltage monitor interrupt is enabled vim = 1, voltage monitor interrupt is disabled vms v oltage m onitor s tatus bit vms = 0, the voltage at the comparator input is below vref vms = 1, the voltage at the comparator input is above vref v dd low threshold middle threshold high threshold vms = 1 low threshold middle threshold high threshold vms = 0 3.0 v 2.6 v 2.2 v 13755 figure 12. internal supply voltage supervisor 1.3 v vmi vms = 1 vms = 0 positive slope negative slope vms = 1 vms = 0 interrupt negative slope interrupt positive slope internal reference level t 13756 figure 13. external input voltage supervisor
t48c893 t48c893 rev. a4, 22-jan-02 17 (82) 3.5 clock generation 3.5.1 clock module the t48c893 contains a clock module with 4 different internal oscillator types: two rc-oscillators, one 4-mhz crystal oscillator and one 32-khz crystal oscillator. the pins osc1 and osc2 are the interface to connect a crystal either to the 4-mhz, or to the 32-khz crystal oscillator. osc1 can be used as input for external clocks or to connect an external trimming resistor for the rc-oscillator 2. all necessary circuitry except the crystal and the trimming resistor is integrated on-chip. one of these oscillator types or an external input clock can be selected to generate the system clock (syscl). in applications that do not require exact timing, it is possible to use the fully integrated rc-oscillator 1 without any external components. the rc-oscillator 1 center frequency tolerance is better than 50%. the rc-oscillator 2 is a trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor attached between osc1 and v dd . in this configuration, the rc-oscillator 2 frequency can be maintained stable to within a tolerance of 15% over the full operating temperature and voltage range. the clock module is programmable via software with the clock management register (cm) and the system configuration register (sc). the required oscillator configuration can be selected with the os1-bit and the os0-bit in the sc-register. a programmable 4-bit divider stage allows the adjustment of the system clock speed. a special feature of the clock management is that an external oscillator may be used and switched on and off via a port pin for the power-down mode. before the external clock is switched off, the internal rc-oscillator 1 must be selected with the ccs-bit and then the sleep mode may be activated. in this state an interrupt can wake up the controller with the rc-oscillator, and the external oscillator can be activated and selected by software. a synchronization stage avoids too short clock periods if the clock source or the clock speed is changed. if an external input clock is selected, a supervisor circuit monitors the external input and generates a hardware reset if the external clock source fails or drops below 500 khz for more than 1 msec. ext. clock exin exout stop rc oscillator2 rcout2 stop r trim 4 ? mhz oscillator 4out stop oscin oscout oscin oscout 32 ? khz oscillator 32out oscin oscout rc oscillator 1 rcout1 control stop in1 in2 cin /2 /2 /2 /2 divider sleep wdl osc ? stop nstop ccs css1 css0 cm: bot ? ? ? os1 os0 subcl syscl sc: * osc1 * osc2 * configurable cin/16 32 khz figure 14. clock module table 4 clock modes mode clock source for syscl clock source for subcl os1 os0 ccs = 1 ccs = 0 1 1 1 rc-oscillator 1 (intern) external input clock c in / 16 2 0 1 rc-oscillator 1 (intern) rc-oscillator 2 with external trimming resistor c in / 16 3 1 0 rc-oscillator 1 (intern) 4-mhz oscillator c in / 16 4 0 0 rc-oscillator 1 (intern) 32-khz oscillator 32 khz
t48c893 rev. a4, 22-jan-02 18 (82) the clock module generates two output clocks. one is the system clock (syscl) and the other the periphery (subcl). the syscl can supply the core and the peripherals and the subcl can supply only the peripherals with clocks. the modes for clock sources are programmable with the os1-bit and os0-bit in the sc- register and the ccs-bit in the cm-register. 3.5.2 oscillator circuits and external clock input stage the t48c893 series consists of four different internal os- cillators: two rc-oscillators, one 4-mhz crystal oscillator, one 32-khz crystal oscillator and one external clock input stage. rc-oscillator 1 fully integrated for timing insensitive applications, it is possible to use the fully integrated rc oscillator 1. it operates without any external components and saves additional costs. the rc ? oscillator 1 center frequency tolerance is better than 50% over the full temperature and voltage range. the basic center frequency of the rc-oscillator 1 is f o 4.0 mhz the rc oscillator 1 is selected by default after power ? on reset. rc oscillator 1 rcout1 stop control rcout1 osc ? stop 13758 figure 15. rc-oscillator 1 external input clock the osc1 can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. additionally the external clock stage contains a supervisory circuit for the input clock. the supervisor function is controlled via the os1, os0-bit in the sc ? register and the ccs ? bit in the cm- register. if the external input clock is missing for more than 1 ms and ccs = 0 is set in the cm-register, the supervisory circuit generates a hardware reset.. ext. input clock exout stop ext. clock rcout1 osc ? stop 13759 exin ccs res osc1 osc2 clock monitor figure 16. external input clock os1 os0 ccs supervisor reset output (res) 1 1 0 enable 1 1 1 disable x 0 x disable rc-oscillator 2 with external trimming resistor the rc-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between osc1 and v dd . in this configuration, the rc-oscillator 2 frequency can be maintained stable to within a tolerance of 15% over the full operating temperature and a voltage range v dd from 2.5 v to 6.0 v. for example: an output frequency at the rc-oscillator 2 of 2 mhz, can be obtained by connecting a resistor r ext = 360 k ? (see figures 17). rc oscillator 2 rcout2 stop rcout2 osc ? stop 13760 r trim osc1 osc2 r ext v dd figure 17. rc-oscillator 2 4-mhz oscillator the t48c893 4-mhz oscillator options need a crystal or ceramic resonator connected to the osc1 and osc2 pins to establish oscillation. all the necessary oscillator circuitry, with the exception of the actual crystal, resonator, c3 and c4 are integrated on-chip.
t48c893 t48c893 rev. a4, 22-jan-02 19 (82) 4 ? mhz oscillator 4out 4out osc1 osc2 * oscin c1 * c2 oscout xtal 4 mhz * configurable stop osc ? stop figure 18. 4-mhz crystal oscillator 4 ? mhz oscillator 4out stop 4out osc ? stop osc1 osc2 * oscin c1 * c2 oscout cer. res * configurable c3 c4 figure 19. ceramic resonator 32-khz oscillator some applications require long-term time keeping or low resolution timing. in this case, an on ? chip, low power 32-khz crystal oscillator can be used to generate both the subcl and the syscl. in this mode, power consumption is greatly reduced. the 32-khz crystal oscillator can not be stopped while the power-down mode is in operation. 32 ? khz oscillator 32out 32out osc1 osc2 * oscin c1 * c2 oscout xtal 32 khz * configurable figure 20. 32-khz crystal oscillator 3.5.3 clock management the clock management register controls the system clock divider and synchronization stage. writing to this register triggers the synchronization cycle. clock management register (cm) auxiliary register address: ? 3 ? hex bit 3 bit 2 bit 1 bit 0 cm: nstop ccs css1 css0 reset value: 1111b nstop n ot stop peripheral clock nstop = 0, stops the peripheral clock while the core is in sleep mode nstop = 1, enables the peripheral clock while the core is in sleep mode ccs c ore c lock s elect ccs = 1, the internal rc-oscillator 1 generates syscl ccs = 0, the 4-mhz crystal oscillator, the 32-khz crystal oscillator, an external clock source or the internal rc-oscillator 2 with the external resistor at osc1 generates syscl dependent on the setting of os0 and os1 in the system configuration register css1 c ore s peed s elect 1 css0 c ore s peed s elect 0 css1 css0 divider note 0 0 16 1 1 8 reset value 1 0 4 0 1 2
t48c893 rev. a4, 22-jan-02 20 (82) system configuration register (sc) primary register address: ? 3 ? hex bit 3 bit 2 bit 1 bit 0 sc: write bot ??? os1 os0 reset value: 1x11b bot b rown- o ut t hreshold bot = 1, low brown-out voltage threshold (1.7 v) bot = 0, high brown-out voltage threshold (2.0 v) os1 o scillator s elect 1 os0 o scillator s elect 0 mode os1 os0 input for subcl selected oscillators 1 1 1 c in / 16 rc ? oscillator 1 and external input clock 2 0 1 c in / 16 rc-oscillator 1 and rc-oscillator 2 3 1 0 c in / 16 rc-oscillator 1 and 4-mhz crystal oscillator 4 0 0 32 khz rc-oscillator 1 and 32-khz crystal oscillator if the bit ccs = 0 in the cm-register the rc-oscillator 1 always stops. 3.6 power-down modes the sleep mode is a shut-down condition which is used to reduce the average system power consumption in applica- tions where the c is not fully utilized. in this mode, the system clock is stopped. the sleep mode is entered via the sleep instruction. this instruction sets the interrupt en- able bit (i) in the condition code register to enable all interrupts and stops the core. during the sleep mode the peripheral modules remain active and are able to generate interrupts. the c exits the sleep mode by carrying out any interrupt or a reset. the sleep mode can only be kept when none of the inter- rupt pending or active register bits are set. the application of the $autosleep routine ensures the correct function of the sleep mode. for standard applications use the $au- tosleep routine to enter the power-down mode. using the sleep instruction instead of the $autosleep fol- lowing an i/o instruction requires to insert 3 non i/o instruction cycles (for example nop nop nop) between the in or out command and the sleep command. the total power consumption is directly proportional to the active time of the c. for a rough estimation of the expected average system current consumption, the fol- lowing formula should be used: i total (v dd ,f syscl ) = i sleep + (i dd t active / t total ) i dd depends on v dd and f syscl . the t48c893 has various power-down modes. during the sleep mode the clock for the marc4 core is stopped. with the nstop-bit in the clock management register (cm) it is programmable if the clock for the on ? chip pe- ripherals is active or stopped during the sleep mode. if the clock for the core and the peripherals is stopped the se- lected oscillator is switched off. an exception is the 32-khz oscillator, if it is selected it runs continously inde- pendent of the nstop-bit. if the oscillator is stopped or the 32 khz oscillator is selected, power consumption is extremely low. table 5 power-down modes mode cpu core osc-stop* brown-out function rc-oscillator 1 rc-oscillator 2 4-mhz oscillator 32-khz oscillator external input clock active run no active run run yes power-down sleep no active run run yes sleep sleep yes stop stop run stop * osc-stop = sleep & nstop & wdl
t48c893 t48c893 rev. a4, 22-jan-02 21 (82) 4 peripheral modules 4.1 addressing peripherals accessing the peripheral modules takes place via the i/o bus (see figure 21). the in or out instructions allow di- rect addressing of up to 16 i/o modules. a dual register addressing scheme has been adopted to enable direct ad- dressing of the ? primary register ? . to address the ? auxiliary register ? , the access must be switched with an ? auxiliary switching module ? . thus a single in (or out) to the module address will read (or write) into the module primary register. accessing the auxiliary register is per- formed with the same instruction preceded by writing the module address into the auxiliary switching module. byte wide registers are accessed by multiple in- (or out-) instructions. for more complex peripheral modules, with a larger number of registers, extended addressing is used. in this case a bank of up to 16 subport registers are indi- rectly addressed with the subport address. the first out-instruction writes the subport address to the sub- address register, the second in- or out-instruction reads data from or writes data to the addressed subport. subaddress reg. subport 0 subport 1 subport fh subport eh i/o bus aux. reg. primary reg. bank of primary regs. primary reg. primary reg. (address pointer) auxiliary sw it ch module i n d i r e c t s u b p o r t a c c e s s d u a l r e g i s t e r a c c e s s s i n g l e r e g i s t e r a c c e s s to other modules address(m2) address(asw) out aux._data address(m2) out prim._data address(m2) out (primary register write) prim._data address(m3) out (primary register write) addr.(sport) addr.(m1) out 1 2 (subport register write) sport_data addr.(m1) out 3 4 5 1 2 3 6 6 4 5 exa mple of qf orth program code addr.(mx) = module mx addr ess aux._data = data to be written into auxiliary register prim._data = data to be written into primary register. addr.(sport) addr.(m1) out 1 2 (subport register read) addr.(m1) in address(m2) address(asw) out address(m2) in (auxiliary register rea d) 4 5 address(m2) in (primary register read) 3 address(m3) in (primary register read) 6 addr.(asw) = auxiliary switch module address addr.(sport) addr.(m1) out 1 2 (subport register write byte) sport_data(lo) addr.(m1) out 2 addr.(sport) addr.(m1) out 1 2 (subport register read byte) addr.(m1) in 2 sport_data(hi) addr.(m1) out addr.(m1) in sport_data(lo) = data to be written into subport (low nibble) sport_data(hi) = data to be written into subport (high nibble) addr.(sport) = subport address address(m2) address(asw) out aux._data(lo) address(m2) out (auxiliary register write byte) 4 5 aux._data(hi) address(m2) out 5 aux. _ data ( lo ) = data to be written into auxiliar y re g ister ( low nibble ) aux._data (hi) = data to be written into auxiliary register(high nibble) ( auxiliary register write ) 13357 (hi) (lo) (lo) = sport_data (low nibble) (hi) = sport_data (high nibble) module asw module m1 module m2 module m3 figure 21. example of i/o addressing
t48c893 rev. a4, 22-jan-02 22 (82) table 6 peripheral addresses port address name write /read reset value register function module type see page 1 p1dat w/r 1xx1b port 1 ? data register / input data m3 22 2 p2dat w/r 1111b port 2 ? data register / pin data m2 23 aux. p2cr w 1111b port 2 ? control register 23 3 sc w 1x11b port 3 ? system configuration register m3 19 cwd r xxxxb watchdog reset m3 29 aux. cm w/r 1111b port 3 ? clock management register m2 18 4 p4dat w/r 1111b port 4 ? data register / pin data m2 26 aux. p4cr w 1111 1111b port 4 ? control register (byte) 26 5 p5dat w/r 1111b port 5 ? data register / pin data m2 25 aux. p5cr w 1111 1111b port 5 ? control register (byte) 25 6 p6dat w/r 1xx1b port 6 ? data register / pin data m2 27 aux p6cr w 1111b port 6 ? control register (byte) 27 7 t12sub w ???? data to timer 1/2 subport m1 20 subport address 0 t2c w 0000b timer 2 control register m1 37 1 t2m1 w 1111b timer 2 mode register 1 m1 38 2 t2m2 w 1111b timer 2 mode register 2 m1 39 3 t2cm w 0000b timer 2 compare mode register m1 40 4 t2co1 w 1111b timer 2 compare register 1 m1 40 5 t2co2 w 1111 1111b timer 2 compare register 2 (byte) m1 40 6 ???? ???? ???? reserved 7 ???? ???? ???? reserved 8 t1c1 w 1111b timer 1 control register 1 m1 30 9 t1c2 w x111b timer 1 control register 2 m1 30 a wdc w 1111b watchdog control register m1 31 b-f reserved 8 asw w 1111b auxiliary / switch register asw 20 9 stb w xxxx xxxxb serial transmit buffer (byte) m2 60 srb r xxxx xxxxb serial receive buffer (byte) 61 aux. sic1 w 1111b serial interface control register 1 59 a sisc w/r 1x11b serial interface status / control register m2 60 aux. sic2 w 1111b serial interface control register 2 59 b t3sub w/r ???? data to / from timer 3 subport m1 20 subport address 0 t3m w 1111b timer 3 mode register m1 48 1 t3cs w 1111b timer 3 clock select register m1 49 2 t3cm1 w 0000b timer 3 compare mode register 1 m1 50 3 t3cm2 w 0000b timer 3 compare mode register 2 m1 50 4 t3co1 w 1111 1111b timer 3 compare register 1 (byte) m1 51 4 t3cp r xxxx xxxxb timer 3 capture register (byte) m1 51 5 t3co2 w 1111 1111b timer 3 compare register 2 (byte) m1 51 6 w 1111b reserved 7 ? f ???? reserved c t3c w 0000b timer 3 control register m3 48 t3st r x000b timer 3 status register m3 49 d ??? ???? reserved e ??? ???? reserved f vmc w 1111b voltage monitor control register m3 15 vmst r xx11b voltage monitor status register m3 15
t48c893 t48c893 rev. a4, 22-jan-02 23 (82) 4.2 bidirectional ports with the exception of port 1 and port 6, all other ports (2, 4 and 5) are 4 bits wide. port 1 and port 6 have a data width of 2 bits (bit 0 and bit 3). all ports may be used for data input or output. all ports are equipped with schmitt trig- ger inputs and a variety of mask options for open drain, open source, full complementary outputs, pull up and pull down transistors. all port data registers (pxdat) are i/o mapped to the primary address register of the respective port address and the port control register (pxcr), to the corresponding auxiliary register. there are five different directional ports available: port 1 2-bit wide bidirectional ports with automatic full bus width direction switching. port 2 4-bit wide bitwise-programmable i/o port. port 5 4-bit wide bitwise-programmable bidirectional port with optional strong pull-ups and program- mable interrupt logic. port 4 4-bit wide bitwise-programmable bidirectional port also provides the i/o interface to timer 2, ssi, voltage monitor input and external interrupt input. port 6 2-bit wide bitwise-programmable bidirectional port also provides the i/o interface to timer 3 and external interrupt input. 4.2.1 bidirectional port 1 in port 1 the data direction register is not independently software programmable, the direction of the complete port being switched automatically when an i/o instruction occurs (see figure 22). the port is switched to output mode via an out instruction and to input via an in instruction. the data written to a port will be stored into the output data latches and appears immediately at the port pin following the out instruction. after reset all output latches are set to ? 1 ? and the port is switched to input mode. an in instruction reads the condition of the associated pins. note: care must be taken when switching the bidirectional port from output to input. the capacitive pin loading at this port in conjunction with the high resistance pull-ups may cause the cpu to read the contents of the output data register rather than the external input state. to avoid this, one should use either of the following programming techniques: use two in-instructions and drop the first data nibble. the first in switches the port from output to input and the drop removes the first invalid nibble. the second in reads the valid pin state. use an out-instruction followed by an in ? instruction. via the out-instruction, the capacitive load is charged or discharged depend- ing on the optional pull-up / pull-down configuration. write a ? 1 ? for pins with pull-up resistors and a ? 0 ? for pins with pull-down resistors. out in reset i/o bus d r s q q nq r master reset p1daty (data out) (direction) bp1y v dd * switched * switched * * * *) mask options v dd static pull-up static pull-down pull-up pull ? down figure 22. bidirectional port 1
t48c893 rev. a4, 22-jan-02 24 (82) 4.2.2 bidirectional port 2 this, and all other bidirectional ports include a bitwise programmable control register (p2cr), which enables the individual programming of each port bit as input or output. it also opens up the possibility of reading the pin condition when in output mode. this is a useful feature for self testing and for serial bus applications. port 2 however, has an increased drive capability and an additional low resistance pull-up/-down transistor mask option. master reset q q bp2y mask options * * p2daty p2cry i/o bus d i/o bus i/o bus * * switched switched v dd * static pull-up (data out) (direction) * s d * s * v dd static pull-down pull-down pull-up figure 23. bidirectional port 2 port 2 data register (p2dat) primary register address: ? 2 ? hex bit 3 * bit 2 bit 1 bit 0 p2dat p2dat3 p2dat2 p2dat1 p2dat0 reset value: 1111b * bit 3 ? > msb, bit 0 ? > lsb port 2 control register (p2cr) auxiliary register address: ? 2 ? hex bit 3 bit 2 bit 1 bit 0 p2cr p2cr3 p2cr2 p2cr1 p2cr0 reset value: 1111b value: 1111b means all pins in input mode code 3 2 1 0 function x x x 1 bp20 in input mode x x x 0 bp20 in output mode x x 1 x bp21 in input mode x x 0 x bp21 in output mode x 1 x x bp22 in input mode x 0 x x bp22 in output mode 1 x x x bp23 in input mode 0 x x x bp23 in output mode
t48c893 t48c893 rev. a4, 22-jan-02 25 (82) 4.2.3 bidirectional port 5 this, and all other bidirectional ports include a bitwise programmable control register (p5cr), which allows the individual programming of each port bit as input or output. it also opens up the possibility of reading the pin condition when in output mode. this is a useful feature for self testing and for serial bus applications. the port pins can also be used as external interrupt inputs (see figu res 24 & 25). the interrupts (int1 and int6) can be masked or independently configured to trigger on ei- ther edge. the interrupt configuration and port direction is controlled by the port 5 control register (p5cr). an additional low resistance pull ? up/ ? down transistor mask option provides an internal bus pull ? up for serial bus ap- plications. the port 5 data register (p5dat) is i/o mapped to the primary address register of address ? 5 ? h and the port 5 control register (p5cr) to the corresponding auxiliary register. the p5cr is a byte-wide register and is config- ured by writing first the low nibble then the high nibble (see section 2.1 ? addressing peripherals ? ). master reset q v dd bp5y mask options * * p5daty i/o bus d in enable i/o bus * * switched switched v dd * static pull-up (data out) * * s * v dd static pull-down pull-up pull-down figure 24. bidirectional port 5 bidir. port data in in_enable bp53 p53m2 p53m1 p52m2 p52m1 p51m2 p51m1 p50m2 p50m1 decoder decoder decoder decoder bidir. port data in in_enable bp52 i/o ? bus bidir. port data in in_enable bp51 i/o ? bus bidir. port data in in_enable bp50 int1 int6 p5cr: 13764 figure 25. port 5 external interrupts
t48c893 rev. a4, 22-jan-02 26 (82) port 5 data register (p5dat) primary register address: ? 5 ? hex bit 3 bit 2 bit 1 bit 0 p5dat p5dat3 p5dat2 p5dat1 p5dat0 reset value: 1111b port 5 control register (p5cr) byte write auxiliary register address: ? 5 ? hex bit 3 bit 2 bit 1 bit 0 p5cr first write cycle p51m2 p51m1 p50m2 p50m1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p53m2 p53m1 p52m2 p52m1 reset value: 1111b p5xm2, p5xm1 ? port 5x interrupt mode/direction code auxiliary address: ? 5 ? hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp50 in input mode ? interrupt disabled x x 1 1 bp52 in input mode ? interrupt disabled x x 0 1 bp50 in input mode ? rising edge interrupt x x 0 1 bp52 in input mode ? rising edge interrupt x x 1 0 bp50 in input mode ? falling edge interrupt x x 1 0 bp52 in input mode ? falling edge interrupt x x 0 0 bp50 in output mode ? interrupt disabled x x 0 0 bp52 in output mode ? interrupt disabled 1 1 x x bp51 in input mode ? interrupt disabled 1 1 x x bp53 in input mode ? interrupt disabled 0 1 x x bp51 in input mode ? rising edge interrupt 0 1 x x bp53 in input mode ? rising edge interrupt 1 0 x x bp51 in input mode ? falling edge interrupt 1 0 x x bp53 in input mode ? falling edge interrupt 0 0 x x bp51 in output mode ? interrupt disabled 0 0 x x bp53 in output mode ? interrupt disabled
t48c893 t48c893 rev. a4, 22-jan-02 27 (82) 4.2.4 bidirectional port 4 the bidirectional port 4 is both a bitwise configurable i/o port and provides the external pins for the timer 2, ssi and the voltage monitor input (vmi). as a normal port, it performs in exactly the same way as bidirectional port 2 (see figure 26). two additional multiplexes allow data and port direction control to be passed over to other inter- nal modules (timer 2, vm or ssi). the i/o-pins for sc and sd line have an additional mode to generate an ssi ? interrupt. all four port 4 pins can be individually switched by the p4cr ? register . figure 26 shows the internal interfaces to bidirectional port 4. master reset q v dd v dd bpxy mask options * * pxdaty i/o bus d i/o bus i/o bus * * switched switched * * s pxcry s q d pxmry pout (direction) pdir intx * * pin v dd static pull-up static pull-down pull-up pull-down figure 26. bidirectional port 4 and port 6 port 4 data register (p4dat) primary register address: ? 4 ? hex bit 3 bit 2 bit 1 bit 0 p4dat p4dat3 p4dat2 p4dat1 p4dat0 reset value: 1111b port 4 control register (p4cr) byte write auxiliary register address: ? 4 ? hex bit 3 bit 2 bit 1 bit 0 p4cr first write cycle p41m2 p41m1 p40m2 p40m1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p43m2 p43m1 p42m2 p42m1 reset value: 1111b p4xm2, p4xm1 ? port 4x interrupt mode/direction code
t48c893 rev. a4, 22-jan-02 28 (82) auxiliary address: ? 4 ? hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp40 in input mode x x 1 1 bp42 in input mode x x 1 0 bp40 in output mode x x 1 0 bp42 in output mode x x 0 1 bp40 enable alternate function (sc for ssi) x x 0 x bp42 enable alternate function (t2o for timer 2) x x 0 0 bp40 enable alternate function (falling edge interrupt input for int3) 1 1 x x bp43 in input mode 1 1 x x bp41 in intput mode 1 0 x x bp43 in output mode 1 0 x x bp41 in output mode 0 1 x x bp43 enable alternate function (sd for ssi) 0 1 x x bp41 enable alternate function (vmi for voltage monitor input) 0 0 x x bp43 enable alternate function (falling edge interrupt input for int3) 0 0 x x bp41 enable alternate function (t2i exter- nal clock input for timer 2) ??? ??? 4.2.5 bidirectional port 6 the bidirectional port 6 is both a bitwise configurable i/o port and provides the external pins for the timer 3. as a normal port, it performs in exactly the same way as bidirectional port 6 ( see figure 26). two additional multi- plexes allow data and port direction control to be passed over to other internal module (timer 3). the i/o-pin for t3i line has an additional mode to generate a timer 3 ? in- terrupt. all two port 6 pins can be individually switched by the p6cr-register . figure 26 shows the internal interfaces to bidirectional port 6. port 6 data register (p6dat) primary register address: ? 6 ? hex bit 3 bit 2 bit 1 bit 0 p6dat p6dat3 ? ? ? ? ? ? p6dat0 reset value: 1xx1b port 6 control register (p6cr) auxiliary register address: ? 6 ? hex bit 3 bit 2 bit 1 bit 0 p6cr p63m2 p63m1 p60m2 p60m0 reset value: 1111b p6xm2, p6xm1 ? port 6x interrupt mode/direction code auxiliary address: ? 6 ? hex write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp60 in input mode 1 1 x x bp63 in intput mode x x 1 0 bp60 in output mode 1 0 x x bp63 in output mode x x 0 x bp60 enable alternate port function (t3o for timer 3) 0 x x x bp63 enable alternate port function (t3i for timer 3)
t48c893 t48c893 rev. a4, 22-jan-02 29 (82) 4.3 universal timer/counter / communication module (utcm) the u niversal t imer/counter/ c ommunication m odule (utcm) consists of three timers (timer 1 ,timer 2, timer 3) and a s ynchronous s erial i nterface (ssi). timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for timer 2, timer 3, the serial interface and the watch- dog function. timer 2 is an 8/12-bit timer with an external clock in- put (t2i) and an output (t2o). timer 3 is an 8-bit timer/counter with its own input (t3i) and output (t3o). the ssi operates as two wire serial interface or as shift register for modulation and demodulation. the modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. there is a multitude of modes in which the timers and the serial interface can work together. demodu ? lator 3 8 ? bit counter 3 capture 3 compare 3/1 compare 3/2 modu ? lator 3 mux mux control watchdog interval / prescaler timer 1 timer 3 modu ? lator 2 4 ? bit counter 2/1 compare 2/1 mux mux dcg 8 ? bit counter 2/2 compare 2/2 control timer 2 mux 8 ? bit shift ? register receive ? buffer transmit ? buffer control ssi scl int4 int5 int2 nrst int3 pout tog2 tog3 t1out subcl syscl from clock module t3o t3i 13765 t2i t2o sc sd i/o bus figure 27. utcm block diagram
t48c893 rev. a4, 22-jan-02 30 (82) 4.3.1 timer 1 the timer 1 is an interval timer which can be used to gen- erate periodical interrupts and as prescaler for timer 2, timer 3, the serial interface and the watchdog function. the timer 1 consists of a programmable 14-stage divider that is driven by either subcl or syscl. the timer output signal can be used as prescaler clock or as subcl and as source for the timer 1 interrupt. because of other system requirements the timer 1 output t1out is synchronized with syscl. therefore in the power -down mode sleep (cpu core ? > sleep and osc-stop ? > yes) the output t1out is stopped (t1out=0). nevertheless the timer 1 can be active in sleep and generate timer 1 interrupts. the interrupt is maskable via the t1im bit and the subcl can be bypassed via the t1bp bit of the t1c2 register. the time interval for the timer output can be programmed via the timer 1 control register t1c1. this timer starts running automatically after any power-on reset ! if the watchdog function is not activated, the timer can be restarted by writing into the t1c1 register with t1rm=1. timer 1 can also be used as a watchdog timer to prevent a system from stalling. the watchdog timer is a 3-bit counter that is supplied by a separate output of timer 1. it generates a system reset when the 3-bit counter overflows. to avoid this, the 3-bit counter must be reset before it overflows. the application software has to accomplish this by reading the cwd register. after power-on reset the watchdog must be activated by software in the $reset initialization routine. there are two watchdog modes, in one mode the watchdog can be switched on and off by software, in the other mode the watchdog is active and locked. this mode can only be stopped by carrying out a system reset. the watchdog timer operation mode and the time interval for the watchdog reset can be programmed via the watchdog control register (wdc). 13766 prescaler 14 bit cl1 watchdog 4 bit mux wdcl t1im t1bp t1mux nrst int2 t1out t1cs syscl subcl figure 28. timer 1 module q5 q1 q2 q3 q4 q6 q8 q8 q11 q11 q14 q14 res cl decoder watchdog mode control mux for interval timer decoder mux for watchdog timer t1rm t1c2 t1c1 t1c0 3 2 wdl wdr wdt1 wdt0 wdc res t1mux subcl t1bp t1im t1im=0 t1im=1 int2 t1out t1c2 reset (nrst) watchdog divider / 8 divider reset t1c1 write of the t1c1 register cl1 13767 wdcl read of the cwd register figure 29. timer 1 and watchdog
t48c893 t48c893 rev. a4, 22-jan-02 31 (82) timer 1 control register 1 (t1c1) address: ? 7 ? hex ? subaddress: ? 8 ? hex bit 3 * bit 2 bit 1 bit 0 t1c1 t1rm t1c2 t1c1 t1c0 reset value: 1111b * bit 3 ? > msb, bit 0 ? > lsb t1rm t imer 1 r estart m ode t1rm = 0, write access without timer 1 restart t1rm = 1, write access with timer 1 restart note: if wdl = 0, timer 1 restart is impossible t1c2 t imer 1 c ontrol bit 2 t1c1 t imer 1 c ontrol bit 1 t1c0 t imer 1 c ontrol bit 0 the three bits t1c[2:0] select the divider for timer 1. the resulting time interval depends on this divider and the timer 1 input clock source. the timer input can be sup- plied by the system clock, the 32khz oscillator or via the clock management. if the clock management generates the subcl, the selected input clock from the rc oscilla- tor, 4mhz oscillator or an external clock is divided by 16. t1c2 t1c1 t1c0 divider time interval with subcl time interval with subcl = 32 khz time interval with syscl = 2/1 mhz 0 0 0 2 subcl / 2 61 s 1 s / 2 s 0 0 1 4 subcl / 4 122 s 2 s / 4 s 0 1 0 8 subcl / 8 244 s 4 s / 8 s 0 1 1 16 subcl / 16 488 s 8 s / 16 s 1 0 0 32 subcl / 32 0.977 ms 16 s / 32 s 1 0 1 256 subcl / 256 7.812 ms 128 s / 256 s 1 1 0 2048 subcl / 2048 62.5 ms 1024 s / 2048 s 1 1 1 16384 subcl / 16384 500 ms 8192 s / 16384 s timer 1 control register 2 (t1c2) address: ? 7 ? hex ? subaddress: ? 9 ? hex bit 3 * bit 2 bit 1 bit 0 t1c2 ? ? ? t1bp t1cs t1im reset value: x111b * bit 3 ? > msb, bit 0 ? > lsb t1bp t imer 1 subcl b y p assed t1bp = 1, tiout = t1mux t1bp = 0, t1out = subcl t1cs t imer 1 input c lock s elect t1cs = 1, cl1 = subcl (see figure 28) t1cs = 0, cl1 = syscl (see figure 28) t1im t imer 1 i nterrupt m ask t1im = 1, disables timer 1 interrupt t1im = 0, enables timer 1 interrupt
t48c893 rev. a4, 22-jan-02 32 (82) watchdog control register (wdc) address: ? 7 ? hex ? subaddress: ? a ? hex bit 3 * bit 2 bit 1 bit 0 wdc wdl wdr wdt1 wdt0 reset value: 1111b * bit 3 ? > msb, bit 0 ? > lsb wdl w atch d og l ock mode wdl = 1, the watchdog can be enabled and disabled by using the wdr-bit wdl = 0, the watchdog is enabled and locked. in this mode the wdr-bit has no effect. after the wdl-bit is cleared, the watchdog is active until a system reset or power-on reset occurs. wdr w atch d og r un and stop mode wdr = 1, the watchdog is stopped / disabled wdr = 0, the watchdog is active / enabled wdt1 w atch d og t ime 1 wdt0 w atch d og t ime 0 both these bits control the time interval for the watchdog reset wdt1 wdt0 divider delay time to reset with subcl = 32 khz delay time to reset with syscl = 2 / 1 mhz 0 0 512 15.625 ms 0.256 ms / 0.512 ms 0 1 2048 62.5 ms 1.024 ms / 2.048 ms 1 0 16384 0.5 s 8.2 ms / 16.4 ms 1 1 131072 4 s 65.5 ms / 131 ms 4.3.2 timer 2 features: 8/12 bit timer for interrupt, square-wave, pulse and duty cycle generation baud-rate generation for the internal shift register manchester and biphase modulation together with the ssi carrier frequency generation and modulation together with the ssi timer 2 can be used as interval timer for interrupt generation, as signal generator or as baud-rate generator and modulator for the serial interface. it consists of a 4-bit and an 8-bit up counter stage which both have compare registers. the 4-bit counter stages of timer 2 are cascadable as 12-bit timer or as 8-bit timer with 4-bit prescaler. the timer can also be configured as 8-bit timer and separate 4-bit prescaler. the timer 2 input can be supplied via the system clock, the external input clock (t2i), the timer 1 output clock, the timer 3 output clock or the shift clock of the serial interface. the external input clock t2i is not synchro- nized with syscl. therefore it is possible to use t imer 2 with a higher clock speed than syscl. furthermore with that input clock the timer 2 operates in the power-down mode sleep (cpu core ? > sleep and osc ? stop ? > yes) as well as in the power-down (cpu core ? > sleep and osc ? stop ? > no). all other clock sources supplied no clock signal in sleep. the 4-bit counter stages of timer 2 have an additional clock output (pout). its output has a modulator stage that allows the generation of pulses as well as the generation and modulation of carrier frequencies. the timer 2 output can modulate with the shift register data output to generate biphase- or manchester-code. if the serial interface is used to modulate a bitstream, the 4-bit stage of timer 2 has a special task. the shift register can only handle bitstream lengths divisible by 8. for other lengths, the 4-bit counter stage can be used to stop the modulator after the right bitcount is shifted out. if the timer is used for carrier frequency modulation, the 4-bit stage works together with an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty cycle. the 8-bit counter is used to en-
t48c893 t48c893 rev. a4, 22-jan-02 33 (82) able and disable the modulator output for a programmable count of pulses. for programming the time interval, the timer has a 4-bit and an 8-bit compare register. for programming the timer function, it has four mode and control registers. the comparator output of stage 2 is controlled by a special compare mode register (t2cm). this register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match event or the counter overflow. this architecture en- ables the timer function for various modes. timer 2 compare data values the timer 2 has a 4-bit compare register (t2co1) and an 8-bit compare register (t2co2). both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. for 12-bit compare data value: m = x +1 0 x 4095 for 8-bit compare data value: n = y +1 0 y 255 for 4-bit compare data value: l = z +1 0 z 15 4 ? bit counter 2/1 res ovf1 compare 2/1 t2co1 cm1 pout ssi pout cl2/2 dcg t2m1 p4cr 8 ? bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm control tog2 int4 biphase ? , manchester ? modulator output mout m2 to modulator 3 t2o timer 2 modulator output ? stage t2m2 so control ssi ssi i/o ? bus t2c cl2/1 t2i syscl t1out tog3 scl i/o ? bus 13776 dcgo figure 30. timer 2 timer 2 modes mode 1: 12-bit compare counter 4-bit counter 4-bit compare res 4-bit register cm1 pout (cl2/1 /16) 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm ? bit t2im t2ctm tog2 int4 cl2/1 13778 dcg t2d1, 0 figure 31. 12-bit compare counter the 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. a compare match signal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. the compare action is program- mable via the compare mode register (t2cm). the 4-bit counter overflow (ovf1) supplies the clock output (pout) with clocks. the duty cycle generator (dcg) has to be bypassed in this mode.
t48c893 rev. a4, 22-jan-02 34 (82) mode 2: 8-bit compare counter with 4-bit programmable prescaler 4-bit counter 4-bit compare res 4-bit register cm1 pout 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm ? bit t2im t2ctm tog2 int4 cl2/1 13778 dcg t2d1, 0 dcgo figure 32. 8-bit compare counter the 4-bit stage is used as programmable prescaler for the 8-bit counter stage. in this mode, a duty cycle stage is also available. this stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%. the 4-bit compare output (cm1) supplies the clock output (pout) with clocks. mode 3/4: 8-bit compare counter and 4-bit programmable prescaler 4-bit counter 4-bit compare res 4-bit register 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm ? bit t2im t2ctm tog2 int4 cl2/2 13779 dcg t2d1, 0 dcgo p41m2, 1 p4cr cm1 pout cl2/1 mux tog3 t1out syscl scl t2cs1, 0 syscl t2i figure 33. 4-/8-bit compare counter in these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. only in the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input (t2i) which is selected via the p4cr register. the 4-bit prescaler is started via activating of mode 3 and stopped and reset in mode 4. changing mode 3 and 4 has no effect for the 8-bit timer stage. the 4-bit stage can be used as prescaler for timer 3, the ssi or to generate the stop signal for modulator 2 and modulator 3. timer 2 output modes the signal at the timer output is generated via modulator 2. in the toggle mode, the compare match event toggles the output t2o. for high resolution duty cycle modulation 8 bits or 12 bits can be used to toggle the output. in the duty cycle burst modulator modes the dcg
t48c893 t48c893 rev. a4, 22-jan-02 35 (82) output is connected to t2o and switched on and off either by the toggle flipflop output or the serial data line of the ssi. modulator 2 also has 2 modes to output the content of the serial interface as biphase or manchester code. the modulator output stage can be configured by the output control bits in the t2m2 register. the modulator is started with the start of the shift register (sir = 0) and stopped either by carrying out a shift register stop (sir = 1) or compare match event of stage 1 (cm1) of timer 2. for this task, timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (scl). 13780 toggle res/set biphase/ manchester modulator t2top t2os2, 1, 0 t2m2 t2o m2 m2 s1 s2 s3 modulator3 re fe omsk ssi control tog2 so dcgo figure 34. timer 2 modulator output stage timer 2 output signals timer 2 output mode 1: toggle mode a: a timer 2 compare match toggles the output flip-flop (m2) ? > t2o 4 000123 4 0123 4 0123 01 input counter 2 t2r counter 2 cmx int4 t2o 13781 figure 35. interrupt timer / square wave generator ? the output toggles with each edge compare match event
t48c893 rev. a4, 22-jan-02 36 (82) timer 2 output mode 1: toggle mode b: a timer 2 compare match toggles the output flip-flop (m2) ? > t2o 4 000123 567 4 0123 56 input counter 2 t2r counter 2 cmx int4 t2o 13782 toggle by start t2o 4095/ 255 figure 36. pulse generator ? the timer output toggles with the timer start if the t2ts-bit is set timer 2 output mode 1: toggle mode c: a timer 2 compare match toggles the output flip-flop (m2) ? > t2o 4 000123 567 4 0123 56 input counter 2 t2r counter 2 cmx ovf2 int4 13783 t2o 4095/ 255 figure 37. pulse generator ? the timer toggles with timer overflow and compare match timer 2 output mode 2: duty cycle burst generator 1: the dcg output signal (dcgo) is given to the output, and gated by the output flip-flop (m2) 1 2012012345012012345678012345678910012345 dcgo counter 2 tog2 m2 t2o counter = compare register (=2) 13784 figure 38. carrier frequency burst modulation with timer 2 toggle flip-flop output
t48c893 t48c893 rev. a4, 22-jan-02 37 (82) timer 2 output mode 3: duty cycle burst generator 2: the dcg output signal (dcgo) is given to the output, and gated by the ssi internal data output (so) 1 201201201201201201201201201201201201201 dcgo counter 2 tog2 so t2o counter = compare register (=2) 13785 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 figure 39. carrier frequency burst modulation with the ssi data output timer 2 output mode 4: biphase modulator: timer 2 modulates the ssi internal data output (so) to biphase code. tog2 sc so t2o 000 0 0011 0101 1111 8-bit sr-data bit 7 bit 0 13786 data: 00110101 figure 40. biphase modulation timer 2 output mode 5: manchester modulator: timer 2 modulates the ssi internal data output (so) to manchester code tog2 sc so t2o 00 0 0011 0101 11 1 1 8-bit sr-data bit 7 bit 0 13787 0 bit 7 bit 0 data: 00110101 figure 41. manchester modulation
t48c893 rev. a4, 22-jan-02 38 (82) timer 2 output mode 7: pwm mode: pulse ? width modulation output on timer 2 output pin (t2o) in this mode the timer overflow defines the period and the compare register defines the duty cycle. during one period only the first compare match occurence is used to toggle the timer output flip-flop, until the overflow all further compare match are ignored. this avoids the situation that changing the compare register causes the occurence of sev- eral compare match during one period. the resolution at the pulse-width modulation timer 2 mode 1 is 12-bit and all other timer 2 modes are 8-bit. 0 0 50 255 100 0 255 0 150 255 0 50 255 0 100 t2r input clock counter 2/2 counter 2/2 ovf2 cm2 int4 t2o load the next compare value t2co2=150 load load t1 t2 t3 t1 t2 tt t t t 13788 figure 42. pwm modulation timer 2 registers timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. all registers are indirectly addressed using extended addressing as described in section ? addressing peripherals ? . the alternate functions of the ports bp41 or bp42 must be selected with the port 4 control register p4cr, if one of the timer 2 modes require an input at t2i/bp41 or an output at t2o/bp42. timer 2 control register (t2c) address: ? 7 ? hex ? subaddress: ? 0 ? hex bit 3 bit 2 bit 1 bit 0 t2c t2cs1 t2cs0 t2ts t2r reset value: 0000b t2cs1 t imer 2 c lock s elect bit 1 t2cs1 t2cs0 input clock (cl 2/1) of counter stage 2/1 t2cs0 t imer 2 c lock s elect bit 0 0 0 system clock (syscl) 0 1 output signal of timer 1 (t1out) 1 0 internal shift clock of ssi (scl) 1 1 output signal of timer 3 (tog3) t2ts t imer 2 t oggle with s tart t2ts = 0, the output flip-flop of timer 2 is not toggled with the timer start t2ts = 1, the output flip-flop of timer 2 is toggled when the timer is started with t2r t2r t imer 2 r un t2r = 0, timer 2 stop and reset t2r = 1, timer 2 run
t48c893 t48c893 rev. a4, 22-jan-02 39 (82) timer 2 mode register 1 (t2m1) address: ? 7 ? hex ? subaddress: ? 1 ? hex bit 3 bit 2 bit 1 bit 0 t2m1 t2d1 t2d0 t2ms1 t2ms0 reset value: 1111b t2d1 t imer 2 d uty cycle bit 1 t2d0 t imer 2 d uty cycle bit 0 t2d1 t2d0 function of duty cycle generator (dcg) additional divider effect 1 1 bypassed (dcgo0) / 1 1 0 duty cycle 1/1 (dcgo1) / 2 0 1 duty cycle 1/2 (dcgo2) / 3 0 0 duty cycle 1/3 (dcgo3) / 4 t2ms1 t imer 2 m ode s elect bit 1 t2ms0 t imer 2 m ode s elect bit 0 mode t2ms1 t2ms0 clock output (pout) timer 2 modes 1 1 1 4-bit counter overflow (ovf1) 12-bit compare counter; the dcg has to be bypassed in this mode 2 1 0 4-bit compare output (cm1) 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 3 0 1 4-bit compare output (cm1) 8-bit compare counter clocked by syscl or the external clock input t2i, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 4 0 0 4-bit compare output (cm1) 8-bit compare counter clocked by syscl or the external clock input t2i, 4-bit prescaler stop and resets duty cycle generator the duty cycle generator generates duty cycles from 25%, 33% or 50%. the frequency at the duty cycle generator output depends on the duty cycle and the timer 2 prescaler setting. the dcg-stage can also be used as additional programmable prescaler for timer 2. dcgin dcgo0 dcgo1 dcgo2 dcgo3 13807 figure 43. dcg output signals
t48c893 rev. a4, 22-jan-02 40 (82) timer 2 mode register 2 (t2m2) address: ? 7 ? hex ? subaddress: ? 2 ? hex bit 3 bit 2 bit 1 bit 0 t2m2 t2top t2os2 t2os1 t2os0 reset value: 1111b t2top t imer 2 t oggle o utput p reset this bit allows the programmer to preset the timer 2 output t2o. t2top = 0, resets the toggle outputs with the write cycle (m2 = 0) t2top = 1, sets toggle outputs with the write cycle (m2 = 1) note: if t2r = 1, no output preset is possible t2os2 t imer 2 o utput s elect bit 2 t2os1 t imer 2 o utput s elect bit 1 t2os0 t imer 2 o utput s elect bit 0 output mode t2os2 t2os1 t2os0 clock output (pout) 1 1 1 1 toggle mode: a timer 2 compare match toggles the output flip-flop (m2) ? > t2o 2 1 1 0 duty cycle burst generator 1: the dcg output signal (dcg0) is given to the output and gated by the output flip-flop (m2) 3 1 0 1 duty cycle burst generator 2: the dcg output signal (dcgo) is given to the output and gated by the ssi in- ternal data output (so) 4 1 0 0 biphase modulator: timer 2 modulates the ssi internal data output (so) to biphase code 5 0 1 1 manchester modulator: timer 2 modulates the ssi inter- nal data output (so) to manchester code 6 0 1 0 ssi output: t2o is used directly as ssi internal data output (so) 7 0 0 1 pwm mode: an 8/12-bit pwm mode 8 0 0 0 not allowed if one of these output modes is used the t2o alternate function of port 4 must also be activated.
t48c893 t48c893 rev. a4, 22-jan-02 41 (82) timer 2 compare and compare mode registers timer 2 has two separate compare registers, t2co1 for the 4-bit stage and t2co2 for the 8-bit stage of timer 2. the timer compares the contents of the compare register current counter value and if it matches it generates an output signal. dependent on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as ssi clock or as a clock for the next counter stage. in the 12-bit timer mode, t2co1 contains bits 0 to 3 and t2co2 bits 4 to 11 of the 12-bit compare value. in all other modes, the two compare registers work independently as a 4- and 8-bit compare register. when asigned to the compare register a compare event will be supressed. timer 2 compare mode register (t2cm) address: ? 7 ? hex ? subaddress: ? 3 ? hex bit 3 bit 2 bit 1 bit 0 t2cm t2otm t2ctm t2rm t2im reset value: 0000b t2otm t imer 2 o verflow t oggle m ask bit t2otm = 0, disable overflow toggle t2otm = 1, enable overflow toggle, a counter overflow (ovf2) toggles output flip-flop (tog2). if the t2otm-bit is set, only a counter overflow can generate an interrupt except on the timer 2 output mode 7. t2ctm t imer 2 c ompare t oggle m ask bit t2ctm = 0, disable compare toggle t2ctm = 1, enable compare toggle, a match of the counter with the compare register toggles out- put flip-flop (tog2). in timer 2 output mode 7 and when the t2ctm-bit is set, only a match of the counter with the compare register can generate an interrupt. t2rm t imer 2 r eset m ask bit t2rm = 0, disable counter reset t2rm = 1, enable counter reset, a match of the counter with the compare register resets the counter t2im t imer 2 i nterrupt m ask bit t2im = 0, disable timer 2 interrupt t2im = 1, enable timer 2 interrupt timer 2 output mode t2otm t2ctm timer 2 interrupt source 1, 2, 3, 4, 5 and 6 0 x compare match (cm2) 1, 2, 3, 4, 5 and 6 1 x overflow (ovf2) 7 x 1 compare match (cm2) timer 2 compare register 1 (t2co1) address: ? 7 ? hex ? subaddress: ? 4 ? hex t2co1 write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b in prescaler mode the clock is bypassed if the compare register t2co1 contains 0. timer 2 compare register 2 (t2co2) byte write address: ? 7 ? hex ? subaddress: ? 5 ? hex t2co2 first write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b second write cycle bit 7 bit 6 bit 5 bit 4 reset value: 1111b
t48c893 rev. a4, 22-jan-02 42 (82) 4.3.3 timer 3 features 2 compare registers capture register edge sensitive input with zero cross detection capa- bility trigger and single action modes output control modes automatically modulation and demodulation modes fsk modulation pulse width modulation (pwm) manchester demodulation together with ssi biphase demodulation together with ssi pulse-width demodulation together with ssi 8 ? bit counter 3 res compare 3/1 t3co1 t3cp t3co2 control t3o cl3 t3i t3ex syscl t1out pout i/o ? bus 13808 compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu ? lator 3 m2 control so tog3 int5 res cm31 t3i t3ex tog2 si sci t3m t3cs i/o ? bus timer 2 ssi ssi cp3 figure 44. timer 3 timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. the timer can be used as event counter, timer and signal generator. its output can be programmed as modulator and demodulator for the serial interface. the two compare registers enable various modes of signal generation, modulation and demodulation. the counter can be driven by internal and external clock sources. for external clock sources, it has a programmable edge-sensitive input which can be used as counter input, capture signal input or trigger input. this timer input is synchronized with syscl. therefore in the power-down mode sleep (cpu core ? > sleep and osc ? stop ? > yes) this timer input is stopped too. the counter is readable via its capture register while it is running. in capture mode, the counter value can be captured by a programmable capture event from the timer 3 input or timer 2 output. a special feature of this timer is the trigger- and single-ac- tion mode. in trigger mode, the counter starts counting triggered by the external signal at its input. in single-ac- tion mode, the counter counts only one time up to the programmed compare match event. these modes are very useful for modulation, demodulation, signal generation, signal measurement and phase controlling. for phase controlling, the timer input is protected against negative voltages and has zero-cross detection capability. timer 3 has a modulator output stage and input functions for demodulation. as modulator it works together with timer 2 or the serial interface. when the shift register is used for modulation the data shifted out of the register is encoded bitwise. in all demodulation modes, the decoded data bits are shifted automatically into the shift register.
t48c893 t48c893 rev. a4, 22-jan-02 43 (82) 8-bit comparator compare register 1 res capture register 8-bit counter 13809 compare register 2 control c31 c32 control t3sm1 nq d t3rm1 t3im1 t3tm1 tog2 t3i t3tm2 t3im2 t3rm2 t3sm2 nq d cl3 t3eim tog3 int5 cm31 cm32 : t3m1 : t3m2 figure 45. counter 3 stage timer / counter modes timer 3 has 6 timer modes and 6 modulator/demodulator modes. the mode is set via the timer 3 mode register t3m. in all these modes, the compare register and the compare- mode register belonging to it define the counter value for a compare match and the action of a compare match. a match of the current counter value with the content of one compare register triggers a counter reset, a timer 3 interrupt or the toggling of the output flip-flop. the compare mode registers t3m1 and t3m2 contain the mask bits for enabling or disabling these actions. the counter can also be enabled to execute single actions with one or both compare registers. if this mode is set the corresponding compare match event is generated only once after the counter start. most of the timer modes use its compare registers alternately. after the start has been activated, the first comparison is carried out via the compare register 1, the second is carried out via the compare register 2, the third is carried out again via the compare register 1 and so on. this makes it easy to generate signals with constant periods and variable duty cycle or to generate signals with variable pulse and space widths. if single-action mode is set for one compare register, the comparison is always carried out after the first cycle via the other compare register. the counter can be started and stopped via the control register t3c. this register also controls the initial level of the output before start. t3c contains the interrupt mask for a t3i input interrupt. via the timer 3 clock-select register, the internal or external clock source can be selected. this register selects also the active edge of the external input. an edge at the external input t3i can generate also an interrupt if the t3eim-bit is set and the timer 3 is stopped (t3r = 0) in the t3c-register. the status of the timer as well as the occurrence of a compare match or an edge detect of the input signal is indicated by the status register t2st. this allows identification of the interrupt source because all these events share only one timer interrupt. timer 3 compare data values the timer 3 has two 8-bit compare registers (t3co1, t3co2). the compare data value can be ? m ? for each of the timer 3 compare registers. the compare data value for the compare registers is: m = x +1 0 x 255
t48c893 rev. a4, 22-jan-02 44 (82) timer 3 ? mode 1: timer / counter the selected clock from an internal or external source increments the 8-bit counter. in this mode, the timer can be used as event counter for external clocks at t3i or as timer for generating interrupts and pulses at t3o. the counter value can be read by the software via the capture register. 0 000123 5 1234 0 0123 12 t3r counter 3 cm31 int5 t3o 13810 3 cm32 figure 46. counter reset with each compare match 4 000123 567 4 0123 56 t3r counter 3 cm31 int5 t3o 13811 toggle by start t3o 89 cl3 cm32 figure 47. counter reset with compare register 2 and toggle with start 0 012345678910012 counter 3 cm31 cm32 t3o 13812 012012012012012012012 01201 toggle by start t3r figure 48. single action of compare register 1
t48c893 t48c893 rev. a4, 22-jan-02 45 (82) timer 3 ? mode 2: timer/counter, ext. trigger restart & ext. capture (with t3i input) the counter is driven by an internal clock source. after starting with t3r, the first edge from the external input t3i starts the counter. the following edges at t3i load the current counter value into the capture register, reset the counter and restart it. the edge can be selected by the programmable edge decoder of the timer input stage. if single-action mode is activated for one or both compare registers the trigger signal restarts the single action. 00000000123456 counter 3 t3ex cm31 cm32 13813 78910012xxx012345678910 012xx t3r xx t3o figure 49. externally triggered counter reset and start combined with single-action mode timer 3 ? mode 3: timer/counter, int. trigger restart & int. capture (with tog2) the counter is driven by an internal or external (t3i) clock source. the output toggle signal of timer 2 resets the counter. the counter value before the reset is saved in the capture register. if single-action mode is activated for one ore both compare registers, the trigger signal restarts the single actions. this mode can be used for frequency measure- ments or as event counter with time gate (see combination mode 10). 0012345678910 counter 3 tog2 t3cp ? register 13814 11 0 1 2 401 t3i 2 3 t3r capture value = 0 capture value = 11 capture value = 4 figure 50. event counter with time gate timer 3 ? mode 4: timer/counter the timer runs as timer/counter in mode 1, but its output t3o is used as output for the timer 2 output signal. timer 3 ? mode 5: timer/counter, ext. trigger restart & ext. capture (with t3i input) the timer 3 runs as timer/counter in mode 2, but its output t3o is used as output for the timer 2 output signal. timer 3 modulator / demodulator modes timer 3 ? mode 6: carrier frequency burst modulation controlled by timer 2 output toggle flip-flop (m2) the timer 3 counter is driven by an internal or external clock source. its compare ? and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. the output toggle flip-flop of timer 2 is used to enable or disable the timer 3 output. timer 2 can be driven by the toggle output signal of timer 3 or any other clock source. (see combination mode 11)
t48c893 rev. a4, 22-jan-02 46 (82) timer 3 ? mode 7: carrier frequency burst modulation controlled by ssi internal output (so) the timer 3 counter is driven by an internal or external clock source. its compare ? and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. the output (so) of the ssi is used to enable or disable the timer 3 output. the ssi should be supplied with the toggle signal of timer 2 (see combination mode 12). timer 3 ? mode 8: fsk modulation with shift register data (so) the two compare registers are used for generating two different time intervals. the ssi internal data output (so) selects which compare register is used for the output frequency generation. a ? 0 ? level at the ssi data output enables the compare register 1. an ? 1 ? level enables compare register 2. the both compare- and compare mode registers must be programmed to generate the two frequencies via the output toggle flip-flop. the ssi can be supplied with the toggle signal of timer 2. the timer 3 counter is driven by an internal or external clock source. the timer 2 counter is driven by the counter 3 (tog3) (see also combination mode 13). 01234012340123 counter 3 cm31 cm32 so 13815 401201201201201201201 20123 t3r 40 t3o 1 01 0 figure 51. fsk modulation timer 3 ? mode 9: pulse-width modulation with the shift register the two compare registers are used for generating two different time intervals. the ssi internal data output (so) selects which compare register is used for the output pulse generation. in this mode both compare- and compare mode registers must be programmed for generating the two pulse widths. it is also useful to enable the single-action mode for extreme duty cycles. timer 2 is used as baudrate generator and for the trigger restart of timer 3. the ssi must be supplied with a toggle signal of timer 2. the counter is driven by an internal or external clock source (see combination mode 7). 000000000 0000 counter 3 cm31 cm32 t3o 13816 000001234567891011121314150 12345 tog2 67 8 1 911 12 10 14 13 0 2 3 14 15 0 0 01 sir so sco t3r figure 52. pulse-width modulation
t48c893 t48c893 rev. a4, 22-jan-02 47 (82) timer 3 ? mode 10: manchester demodulation / pulse-width demodulation for manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. these edges are evaluated by the demodulator stage. the timer stage is used to generate the shift clock for the ssi. the compare register 1 match event defines the correct moment for shifting the state from the input t3i as the decoded bit into shift register ? after that the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. the compare register 2 can also be used to detect a time-out error and handle it with an interrupt routine (see also combination mode 8). 1011100 110 11 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 synchronize manchester demodulation mode timer 3 mode t3ex si sr ? data 13817 t3i cm31=sci 100110 figure 53. manchester demodulation timer 3 ? mode 11: biphase demodulation in the biphase demodulation mode, the timer operates like in manchester demodulation mode. the difference is that the bits are decoded via a toggle flip-flop. this flip-flop samples the edge in the middle of the bitframe and the compare register 1 match event shifts the toggle flip-flop output into shift register (see also combined mode 9). 011 1 1 01 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 synchronize biphase demodulation mode timer 3 mode t3ex q1=si cm31=sci sr ? data 13818 0000 t3i reset counter 3 101010 figure 54. biphase demodulation
t48c893 rev. a4, 22-jan-02 48 (82) timer 3 ? mode 12: timer / counter with external capture mode (t3i) the counter is driven by an internal clock source and an edge at the external input t3i loads the counter value into the capture register. the edge can be selected with the programmable edge detector of the timer input stage. this mode can be used for signal and pulse measurements. 01234567891011 counter 3 t3cp ? register 13819 15 t3i t3r capture value = x capture value = 17 capture value = 35 0 121314 16 20 171819 22 21 23 27 242526 29 28 30 34 313233 36 35 37 41 383940 figure 55. external capture mode timer 3 modulator for carrier frequency burst modulation if the output stage operates as pulse-width modulator for the shift register the output can be stopped with stage 1 of timer 2. for this task, the timer mode 3 must be used and the prescaler must be supplied by the internal shift clock of the shift register. the modulator can be started with the start of the shift register (sir=0) and stopped either by a shift register stop (sir=1) or compare match event of stage 1 of timer 2. for this task, the timer 2 must be used in mode 3 and the pre- scaler stage must be supplied by the internal shift clock of the shift register. 13820 t3 set res t3o t3top omsk tog3 so ssi/ control m2 m3 mux t3m 0 1 2 3 timer 3 mode t3o 6 mux 1 7 mux 2 9 mux 3 other mux 0 figure 56. modulator 3 timer 3 demodulator for biphase, manchester and pulse-width-modulated signals the demodulator stage of timer 3 can be used to decode biphase, manchester and pulse-width-coded signals demodulator 3 t3ex res cm31 counter 3 reset counter 3 control sci si t3i t3m 13821 figure 57. timer 3 demodulator 3
t48c893 t48c893 rev. a4, 22-jan-02 49 (82) timer 3 registers timer 3 mode register (t3m) address: ? b ? hex ? subaddress: ? 0 ? hex bit 3 bit 2 bit 1 bit 0 t3m t3m3 t3m2 t3m1 t3m0 reset value: 1111b t3m3 t imer 3 m ode select bit 3 t3m2 t imer 3 m ode select bit 2 t3m1 t imer 3 m ode select bit 1 t3m0 t imer 3 m ode select bit 0 mode t3m3 t3m2 t3m1 t3m0 timer 3 modes 1 1 1 1 1 timer / counter with a read access 2 1 1 1 0 timer / counter, external capture & external trigger restart mode (t3i) 3 1 1 0 1 timer / counter, internal capture & internal trigger restart mode (tog2) 4 1 1 0 0 timer / counter mode 1 without output (t2o ? > t3o) 5 1 0 1 1 timer / counter mode 2 without output (t2o ? > t3o) 6 1 0 1 0 burst modulation with timer 2 (m2) 7 1 0 0 1 burst modulation with shift register (so) 8 1 0 0 0 fsk modulation with shift register (so) 9 0 1 1 1 pulse-width modulation with shift register (so) & timer 2 (tog2), internal trigger restart (sco) ? > counter reset 10 0 1 1 0 manchester demodulation / pulse-width demodulation * (t2o ? > t3o) 11 0 1 0 1 biphase demodulation * (t2o ? > t3o) 12 0 1 0 0 timer / counter with external capture mode (t3i) 13 0 0 1 1 not allowed 14 0 0 1 0 not allowed 15 0 0 0 1 not allowed 16 0 0 0 0 not allowed * in this mode, the ssi can be used only as demodulator (8-bit nrz rising edge). all other ssi modes are not allowed. timer 3 control register 1 (t3c) write primary register address: ? c ? hex ? write bit 3 bit 2 bit 1 bit 0 t3c write t3eim t3top t3ts t3r reset value: 0000b t3eim t imer 3 e dge i nterrupt m ask t3eim = 0, disables the interrupt when an edge event for timer 3 occurs (t3i) t3eim = 1, enables the interrupt when an edge event for timer 3 occurs (t3i) t3top t imer 3 t oggle o utput p reset t3top = 0, sets toggle output (m3) to ? 0 ? t3top = 1, sets toggle output (m3) to ? 1 ? note: if t3r = 1, no output preset is possible t3ts t imer 3 t oggle with s tart t3ts = 0, timer 3 output is not toggled during the start t3ts = 1, timer 3 output is toggled if it is started with t3r t3r t imer 3 r un t3r = 0, timer 3 stop and reset t3r = 1, timer 3 run
t48c893 rev. a4, 22-jan-02 50 (82) timer 3 status register 1 (t3st) read primary register address: ? c ? hex ? read bit 3 bit 2 bit 1 bit 0 t3st read ? ? ? t3ed t3c2 t3c1 reset value: x000b t3ed t imer 3 e dge d etect this bit will be set by the edge-detect logic of timer 3 input (t3i) t3c2 t imer 3 c ompare 2 this bit will be set when a match occurs between counter 3 and t3co2 t3c1 t imer 3 c ompare 1 this bit will be set when a match occurs between counter 3 and t3co1 note: the status bits t3c1, t3c2 and t3ed will be reset after a read access to t3st. timer 3 clock select register (t3cs) address: ? b ? hex ? subaddress: ? 1 ? hex bit 3 bit 2 bit 1 bit 0 t3cs t3e1 t3e0 t3cs1 t3cs0 reset value: 1111b t3e1 t imer 3 e dge select bit 1 t3e1 t3e0 timer 3 input edge select (t3i) t3e0 t imer 3 e dge select bit 0 1 1 ? ? ? 1 0 positive edge at t3i pin 0 1 negative edge at t3i pin 0 0 each edge at t3i pin t3cs1 t imer 3 c lock s ource select bit 1 t3cs1 tcs0 counter 3 input signal (cl3) t3cs0 t imer 3 c lock s ource select bit 0 1 1 system clock (syscl) 1 0 output signal of timer 2 (pout) 0 1 output signal of timer 1 (t1out) 0 0 external input signal from t3i edge detect timer 3 compare- and compare mode register timer 3 has two separate compare registers t3co1 and t3co2 for the 8-bit stage of timer 3. the timer compares the content of the compare register with the current counter value. if both match, it generates a signal. this signal can be used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as ssi clock or as clock for the next counter stage. for each compare register an compare-mode register exists. this registers contain mask bits to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a compare match of the corresponding compare register. the mask bits for activating the single-action mode can also be located in the compare mode registers. when assigned to the compare register a compare event will be supressed.
t48c893 t48c893 rev. a4, 22-jan-02 51 (82) timer 3 compare mode register 1 (t3cm1) address: ? b ? hex ? subaddress: ? 2 ? hex bit 3 bit 2 bit 1 bit 0 t3cm1 t3sm1 t3tm1 t3rm1 t3im1 reset value: 0000b t3sm1 t imer 3 s ingle action m ask bit 1 t3sm1 = 0, disables single-action compare mode t3sm1 = 1, enables single-compare mode. after this bit is set, the compare register (t3co1) is used until the next compare match. t3tm1 t imer 3 compare t oggle action m ask bit 1 t3tm1 = 0, disables compare toggle t3tm1 = 1, enables compare toggle. a match of counter 3 with the compare register (t3co1) toggles the output flip-flop (tog3). t3rm1 t imer 3 r eset m ask bit 1 t3rm1 = 0, disables counter reset t3rm1 = 1, enables counter reset. a match of counter 3 with the compare register (t3co1) resets the counter 3. t3im1 t imer 3 i nterrupt m ask bit 1 t3rm1 = 0, disables timer 3 interrupt for t3co1 register. t3rm1 = 1, enables timer 3 interrupt for t3co1 register. t3cm1 contains the mask bits for the match event of the counter 3 compare register 1 timer 3 compare mode register 2 (t3cm2) address: ? b ? hex ? subaddress: ? 3 ? hex bit 3 bit 2 bit 1 bit 0 t3cm2 t3sm2 t3tm2 t3rm2 t3im2 reset value: 0000b t3sm2 t imer 3 s ingle action m ask bit 2 t3sm2 = 0, disables single-action compare mode t3sm2 = 1, enables single-compare mode. after this bit is set, the compare register (t3co2) is used until the next compare match. t3tm2 t imer 3 compare t oggle action m ask bit 2 t3tm2 = 0, disables compare toggle t3tm2 = 1, enables compare toggle. a match of counter 3 with the compare register (t3co2) toggles the output flip-flop (tog3). t3rm2 t imer 3 r eset m ask bit 2 t3rm2 = 0, disables counter reset t3rm2 = 1, enables counter reset. a match of counter 3 with the compare register (t3co2) resets the counter 3. t3im2 t imer 3 i nterrupt m ask bit 2 t3rm2 = 0, disables timer 3 interrupt for t3co2 register. t3rm2 = 1, enables timer 3 interrupt for t3co2 register. t3cm2 contains the mask bits for the match event of counter 3 compare register 2 the compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program output signal. the single-action mask can also be used in this mode. it starts operating after the timer started with t3r.
t48c893 rev. a4, 22-jan-02 52 (82) timer 3 compare register 1 (t3co1) byte write address: ? b ? hex ? subaddress: ? 4 ? hex high nibble t3co1 second write cycle bit 7 bit 6 bit 5 bit 4 reset value: 1111b low nibble first write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b timer 3 compare register 2 (t3co2) byte write address: ? b ? hex ? subaddress: ? 5 ? hex high nibble t3co2 second write cycle bit 7 bit 6 bit 5 bit 4 reset value: 1111b low nibble first write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b timer 3 capture register the counter content can be read via the capture register. there are two ways to use the capture register. in modes 1 and 4, it is possible to read the current counter value directly out of the capture register. in the capture modes 2, 3, 5 and 12, a capture event like an edge at the timer 3 input or a signal from timer 2 stores the current counter value into the capture register. this counter value can be read from the capture register. timer 3 capture register (t3cp) byte read address: ? b ? hex ? subaddress: ? 4 ? hex high nibble t3cp first read cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb low nibble second read cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb
t48c893 t48c893 rev. a4, 22-jan-02 53 (82) 4.3.4 synchronous serial interface (ssi) ssi features: 2- and 3-wire nrz 2-wire mode (i 2 c compatible) (additional internal 2-wire link for multi-chip packaging solutions) with timer 2: biphase modulation manchester modulation pulse-width demodulation burst modulation with timer 3: pulse-width modulation (pwm) fsk modulation biphase demodulation manchester demodulation pulse-width demodulation pulse position demodulation ssi peripheral configuration the synchronous serial interface (ssi) can be used either for serial communication with external devices such as eeproms, shift registers, display drivers, other microcontrollers, or as a means for generating and capturing on-chip serial streams of data. external data communication takes place via the port 4 (bp4) multi-functional port which can be software configured by writing the appropriate control word into the p4cr register. the ssi can be configured in any one of the following ways: a) 2-wire external interface for bidirectional data communication with one data terminal and one shift clock. the ssi uses the port bp43 as a bidirectional serial data line (sd) and bp40 as shift clock line (sc). b) 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (si), a serial output data terminal (so) and a shift clock (sc). the ssi uses bp40 as shift clock (sc), while the serial data input (si) is applied to bp43 (configured in p4cr as input!). serial output data (so) in this case is passed through to bp42 (configured in p4cr to t2o) via the timer 2 output stage (t2m2 configured in mode 6). c) timer/ssi combined modes ? the ssi used together with timer 2 or t imer 3 is capable of performing a variety of data modulation and demodulation functions (see timer section). the modulating data is converted by the ssi into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. serial demodulated data can be serially captured in the ssi and read by the controller. in the timer 3 modes 10 and 11 (demodulation modes) the ssi can only be used as demodulator. d) multi-chip link (mcl) ? the ssi can also be used as an interchip data interface for use in single package multi ? chip modules or hybrids. for such applications, the ssi is provided with two dedicated pads (mcl_sd and mcl_sc) which act as a two-wire chip-to-chip link. the mcl can be activated by the mcl control bit. should these mcl pads be used by the ssi, the standard sd and sc pins are not required and the corresponding port 4 ports are available as conventional data ports.
t48c893 rev. a4, 22-jan-02 54 (82) 13822 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc sc control stb srb si timer 2 / timer 3 output int3 sc i/o ? bus i/o-bus ssi-control tog2 pout t1out syscl so si mcl_sc sd mcl_sd transmit buffer receive buffer sci /2 figure 58. block diagram of the synchronous serial interface general ssi operation the ssi is comprised essentially of an 8-bit shift register with two associated 8-bit buffers ? the receive buffer (srb) for capturing the incoming serial data and a trans- mit buffer (stb) for intermediate storage of data to be serially output. both buffers are directly accessable by software. transferring the parallel buf fer data into and out of the shift register is controlled automatically by the ssi control, so that both single byte transfers or continuous bit streams can be supported. the ssi can generate the shift clock (sc) either from one of several on-chip clock sources or accept an external clock. the external shift clock is output on, or applied to the port bp40. selection of an external clock source is performed by the serial clock direction control bit (scd). in the combinational modes, the required clock is selected by the corresponding timer mode. the ssi can operate in three data transfer modes ? synchronous 8-bit shift mode, i 2 c compatible 9-bit shift modes or 8-bit pseudo i 2 c protocol (without acknowl- edge-bit). external ssi clocking is not supported in these modes. the ssi should thus generate and has full control over the shift clock so that it can always be regarded as an i 2 c bus master device. all directional control of the external data port used by the ssi is handled automatically and is dependent on the transmission direction set by the serial data direction (sdd) control bit. this control bit defines whether the ssi is currently operating in transmit (tx) mode or receive (rx) mode. serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. in the 9-bit i 2 c mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see i 2 c protocol). at the beginning of every telegram, the ssi control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. at the same time, incoming data is shifted into the shift register input. this incoming data is automatically loaded into the receive buffer when the complete telegram has been received. data can, if required thus be simultaneously received and transmitted. before data can be transferred, the ssi must first be activated. this is performed by means of the ssi reset control (sir) bit. all further operation then depends on the data directional mode (tx/rx) and the present status of the ssi buffer registers shown by the serial interface ready status flag (srdy). this srdy flag indicates the (empty/full) status of either the transmit buffer (in tx mode), or the receive buffer (in rx mode). the control logic ensures that data shifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (srdy = 0). the srdy status will then automatically be set back to ? 1 ? and data shifting resumed as soon as the application software loads the new data into the transmit register (in tx mode) or frees the shift register by reading it into the receive buffer (in rx mode). a further activity status (act) bit indicates the present status of the serial communication. the act bit remains high for the duration of the serial telegram or if i 2 c stop or start conditions are currently being generated. both the current srdy and act status can be read in the ssi status register. to deactivate the ssi, the sir bit must be set high.
t48c893 t48c893 rev. a4, 22-jan-02 55 (82) 8-bit synchronous mode sc sc data 13823 sd/to2 110 101 00 bit 7 bit 0 110 101 00 bit 7 bit 0 data: 00110101 (rising edge) (falling edge) figure 59. 8-bit synchronous mode in the 8-bit synchronous mode, the ssi can operate as either a 2- or 3-wire interface (see ssi peripheral configuration). the serial data (sd) is received or transmitted in nrz format, synchronised to either the rising or falling edge of the shift clock (sc). the choice of clock edge is defined by the serial mode control bits (sm0,sm1). it should be noted that the transmission edge refers to the sc clock edge with which the sd changes. to avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. when used together with one of the timer modulator or demodulator stages, the ssi must be set in the 8-bit synchronous mode 1. in rx mode, as soon as the ssi is activated (sir= 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. this first telegram is automatically transferred into the receive buffer and the srdy set to 0 indicating that the receive buffer contains valid data. at the same time an interrupt (if enabled) is generated. the ssi then continues shifting in the following 8-bit telegram. if, during this time the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer and the ssi will continue clocking in the next telegram. should, however, the first telegram not have been read (srdy=1), then the ssi will stop, temporarily holding the second telegram in the shift register until a certain point of time when the controller is able to service the receive buffer. in this way no data is lost or overwritten. deactivating the ssi (sir=1) in mid ? telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. this can be used for clocking in a data telegram of less than 8 bits in length. care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivating the ssi (sir=1) and terminating the reception. after termination, the shift register contents will overwrite the receive buffer. 7654321 0 765432107654321 0 msb lsb tx data 1 tx data 2 tx data 3 msb lsb msb lsb write stb (tx data 2) write stb (tx data 3) write stb (tx data 1) sc sd sir srdy interrupt (ifn = 0) interrupt (ifn = 1) act 13824 figure 60. example of 8-bit synchronous transmit operation
t48c893 rev. a4, 22-jan-02 56 (82) 43210 76543210 msb lsb rx data 1 rx data 2 rx data 3 msb lsb msb lsb read srb (rx data 2) read srb (rx data 3) read srb (rx data 1) sc sd sir srdy interrupt (ifn = 0) interrupt (ifn = 1) act 13825 765 43210 765 7654 figure 61. example of 8-bit synchronous receive operation 9-bit shift mode (i 2 c compatible) in the 9-bit shift mode, the ssi is able to handle the i 2 c protocol (described below). it always operates as an i 2 c master device, i.e., sc is always generated and output by the ssi. both the i 2 c start and stop conditions are auto- matically generated whenever the ssi is activated or deactivated by the sir ? bit. in accordance with the i 2 c protocol, the output data is always changed in the clock low phase and shifted in on the high phase. before activating the ssi (sir=0) and commencing an i 2 c dialog, the appropriate data direction for the first word must be set using the sdd control bit. the state of this bit controls the direction of the data port (bp43 or mcl_sd). once started, the 8 data bits are, depending on the selected direction, either clocked into or out of the shift register. during the 9th clock period, the port direction is automatically switched over so that the corresponding acknowledge bit can be shifted out or read in. in transmit mode, the acknowledge bit received from the slave device is captured in the ssi status register (tack ) where it can be read by the controller. and in receive mode, the state of the acknowledge bit to be returned to the slave device is predetermined by the ssi status register (rack ). changing the directional mode (tx/rx) should not be performed during the transfer of an i 2 c telegram. one should wait until the end of the telegram which can be detected using the ssi interrupt (ifn =1) or by interrogating the act status. a 9-bit telegram, once started will always run to completion and will not be prematurely terminated by the sir bit. so, if the sir ? bit is set to ? 1 ? in mit telegram, the ssi will complete the current transfer and terminate the dialog with an i 2 c stop condition.
t48c893 t48c893 rev. a4, 22-jan-02 57 (82) 7654321 76543210a msb lsb tx data 1 tx data 2 msb lsb write stb (tx data 1) sc sd srdy act interrupt (ifn = 0) interrupt (ifn = 1) 13826 0a write stb (tx data 2) sir sdd start stop figure 62. example of i 2 c transmit dialog 7654321 76543210 a msb lsb tx data 1 rx data 2 msb lsb write stb (tx data 1) sc sd srdy act interrupt (ifn = 0) interrupt (ifn = 1) 13827 0a read srb (rx data 2) sir sdd start stop figure 63. example of i 2 c receive dialog 8-bit pseudo i 2 c mode in this mode, the ssi exhibits all the typical i 2 c opera- tional features except for the acknowledge-bit which is never expected or transmitted. i 2 c bus protocol the i 2 c protocol constitutes a simple 2-wire bidirectional communication highway via which devices can communicate control and data information. although the i 2 c protocol can support multi ? master bus
t48c893 rev. a4, 22-jan-02 58 (82) configurations, the ssi, in i 2 c mode is intended for use purely as a master controller on a single master bus system. so all reference to multiple bus control and bus contention will be omitted at this point. all data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. normally the communication channel is opened with a so-called start condition, which initializes all devices connected to the bus. this is then followed by a data telegram, transmitted by the master controller device. this telegram usually contains an 8-bit address code to activate a single slave device connected onto the i 2 c bus. each slave receives this address and compares it with it ? s own unique address. the addressed slave device, if ready to receive data will respond by pulling the sd line low during the 9th clock pulse. this represents a so-called i 2 c acknowledge. the controller on detecting this affirmative acknowledge then opens a connection to the required slave. data can then be passed back and forth by the master controller, each 8-bit telegram being acknowledged by the respective recipient. the communication is finally closed by the master device and the slave device put back into standby by applying a stop condition onto the bus. (2) (1) (4) (4) (3) (1) start condition data valid data change data valid stop condition 13832 sc sd figure 64. i 2 c bus protocol 1 bus not busy (1) both data and clock lines remain high. start data transfer (2) a high to low transition of the sd line while the clock (sc) is high defines a start condition. stop data transfer (3) a low to high transition of the sd line while the clock (sc) is high defines a stop condition. data valid (4) the state of the data line represents valid data when, after start condition, the data line is stable for the duration of the high period of the clock signal. acknowledge all address and data words are serially transmitted to and from device in eight ? bit words. the receiving device returns a zero on the data line during the ninth clock cycle to acknowledge word receipt. 13833 sc sd start 1n89 1st bit 8th bit ack stop figure 65. i 2 c bus protocol 2
t48c893 t48c893 rev. a4, 22-jan-02 59 (82) ssi interrupt the ssi interrupt int3 can be generated either by an ssi buffer register status (i.e., transmit buffer empty or receive buffer full) end of ssi data telegram or on the falling edge of the sc/sd pins on port 4 (see p4cr). ssi interrupt selection is performed by the i nterrupt f unctio n control bit (ifn). the ssi interrupt is usually used to synchronize the software control of the ssi and inform the controller of the present ssi status. the port 4 interrupts can be used together with the ssi or, if the ssi itself is not required, as additional external interrupt sources. in either case this interrupt is capable of waking the controller out of sleep mode. to enable and select the ssi relevant interrupts use the ssi interrupt mask (sim) and the interrupt function (ifn) while the port 4 interrupts are enabled by setting appropriate control bits in p4cr register. modulation and demodulation if the shift register is used together with timer 2 or timer 3 for modulation or demodulation purposes, the 8-bit synchronous mode must be used. in this case, the unused port 4 pins can be used as conventional bidirectional ports. the modulation and demodulation stages, if enabled, operate as soon as the ssi is activated (sir=0) and cease when deactivated (sir=1). due to the byte-orientated data control, the ssi when running normally generates serial bit streams which are submultiples of 8 bits. an ssi output masking (omsk) function permits, however, the generation of bit streams of any length. the omsk signal is derived indirectly from the 4-bit prescaler of the timer 2 and masks out a programmable number of unrequired trailing data bits during the shifting out of the final data word in the bit stream. the number of non-masked data bits is defined by the value pre-programmed in the prescaler compare register. to use output masking, the modulator stop mode bit (msm) must be set to ? 0 ? before programming the final data word into the ssi transmit buffer. this in turn, enables shift clocks to the prescaler when this final word is shifted out. on reaching the compare value, the prescaler triggers the omsk signal and all following data bits are blanked. internal 2-wire multi-chip link two additional on-chip pads (mcl_sc and mcl_sd) for the sc and the sd line can be used as chip-to-chip link for multi-chip applications. these pads can be activated by setting the mcl-bit in the sisc-register. they are also used as interface to the internal data eeprom scl sda mcl_sc mcl_sd u505m v dd bp40/sc bp10 bp43/sd bp13 multi chip link v ss t48c893 figure 66. multi-chip link 13834 8-bit shift register msb lsb shift_cl so control si timer 2 output ssi-control so compare 2/1 4-bit counter 2/1 cl2/1 scl cm1 omsk sc tog2 pout t1out syscl /2 figure 67. ssi output masking function
t48c893 rev. a4, 22-jan-02 60 (82) serial interface registers serial interface control register 1 (sic1) auxiliary register address: ? 9 ? hex bit 3 bit 2 bit 1 bit 0 sic1 sir scd scs1 scs0 reset value: 1111b sir s erial i nterface r eset sir = 1, ssi inactive sir = 0, ssi active scd s erial c lock d irection scd = 1, sc line used as output scd = 0, sc line used as input note: this bit has to be set to ? 1 ? during the i 2 c mode and the timer 3 mode 10 or 11 scs1 s erial c lock source s elect bit 1 scs1 scs0 internal clock for ssi scs0 s erial c lock source s elect bit 0 1 1 syscl / 2 1 0 t1out / 2 note: with scd = ? 0 ? the bits scs1 0 1 pout / 2 and scs0 are insignificant 0 0 tog2 / 2 ? in transmit mode (sdd = 1) shifting starts only if the transmit buffer has been loaded (srdy = 1). ? setting sir-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). ? in i 2 c modes, writing a 0 to sir generates a start condition and writing a 1 generates a stop condition. serial interface control register 2 (sic2) auxiliary register address: ? a ? hex bit 3 bit 2 bit 1 bit 0 sic2 msm sm1 sm0 sdd reset value: 1111b msm m odular s top m ode msm = 1, modulator stop mode disabled (output masking off) msm = 0, modulator stop mode enabled (output masking on) ? used in modulation modes for generating bit streams which are not sub-multiples of 8 bit. sm1 s erial m ode control bit 1 mode sm1 sm0 ssi mode sm0 s erial m ode control bit 0 1 1 1 8-bit nrz-data changes with the rising edge of sc 2 1 0 8-bit nrz-data changes with the falling edge of sc 3 0 1 9-bit two-wire i 2 c compatible 4 0 0 8-bit two-wire pseudo i 2 c compatible (no acknowledge) sdd s erial d ata d irection sdd = 1, transmit mode ? sd line used as output (transmit data). srdy is set by a transmit buffer write access. sdd = 0, receive mode ? sd line used as input (receive data). srdy is set by a receive buffer read access note: sdd controls port directional control and defines the reset function for the srdy ? flag
t48c893 t48c893 rev. a4, 22-jan-02 61 (82) serial interface status and control register (sisc) primary register address: ? a ? hex bit 3 bit 2 bit 1 bit 0 sisc write mcl rack sim ifn reset value: 1111b sisc read ? ? ? tack act srdy reset value: xxxxb mcl m ulti- c hip l ink activation mcl = 1, multi-chip link disabled. this bit has to be set to ? 0 ? during transactions to/from the internal eeprom mcl = 0, connnects sc and sd additional to the internal multi-chip link pads rack r eceive ack nowledge status/control bit for i 2 c mode rack = 0, transmit acknowledge in next receive telegram rack = 1, transmit no acknowledge in last receive telegram tack t ransmit ack nowledge status/control bit for i 2 c mode tack = 0, acknowledge received in last transmit telegram tack = 1, no acknowledge received in last transmit telegram sim s erial i nterrupt m ask sim = 1, disable interrupts sim = 0, enable serial interrupt. an interrupt is generated. ifn i nterrupt f u n ction ifn = 1, the serial interrupt is generated at the end of telegram ifn = 0, the serial interrupt is generated when the srdy goes low (i.e., buffer becomes empty/full in transmit/receive mode) srdy s erial interface buffer r ea dy status flag srdy = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full srdy = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty act transmission act ive status flag act = 1, transmission is active, i.e., serial data transfer. stop or start conditions are currently in progress. act = 0, transmission is inactive serial transmit buffer (stb) ? byte write primary register address: ? 9 ? hex stb first write cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb second write cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb the stb is the transmit buffer of the ssi. the ssi transfers the transmit buffer into the shift register and starts shifting with the most significant bit.
t48c893 rev. a4, 22-jan-02 62 (82) serial receive buffer (srb) ? byte read primary register address: ? 9 ? hex srb first read cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb second read cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb the srb is the receive buffer of the ssi. the shift register clocks serial data in (most significant bit first) and loads content into the receive buffer when complete telegram has been received. 4.3.5 combination modes the utcm consists of two timers (timer 2 and timer 3) and a serial interface. there is a multitude of modes in which the timers and serial interface can work together. the 8-bit wide serial interface operates as shift register for modulation and demodulation. the modulator and demodu- lator units work together with the timers and shift the data bits into or out of the shift register. combination mode timer 2 and ssi 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 pout cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm timer 2 ? control tog2 int4 biphase ? , manchester ? modulator output mout t2o timer 2 modulator output ? stage t2m2 so control t2c cl2/1 t2i syscl t1out tog3 scl i/o ? bus 13836 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc scli control stb srb si output int3 i/o ? bus ssi ? control tog2 pout t1out syscl mcl_sc mcl_sd transmit buffer receive buffer cm1 i/o ? bus pout so scl sc sd dcgo tog2 figure 68. combination timer 2 and ssi
t48c893 t48c893 rev. a4, 22-jan-02 63 (82) combination mode 1: burst modulation ssi mode 1: 8-bit nrz and internal data so output to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler and dcg timer 2 output mode 3: duty cycle burst generator 1 201201201201201201201201201201201201201 dcgo counter 2 tog2 so t2o counter = compare register (=2) 13785 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 figure 69. carrier frequency burst modulation with the ssi internal data output combination mode 2: biphase modulation 1 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler timer 2 output mode 4: the modulator 2 of timer 2 modulates the ssi internal data output to biphase code tog2 sc so t2o 000 0 0011 0101 1111 8-bit sr-data bit 7 bit 0 13786 data: 00110101 figure 70. biphase modulation 1 combination mode 3: manchester modulation 1 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler timer 2 output mode 5: the modulator 2 of timer 2 modulates the ssi internal data output to manchester code tog2 sc so t2o 00 0 0011 0101 11 1 1 8-bit sr-data bit 7 bit 0 13787 0 bit 7 bit 0 data: 00110101 figure 71. manchester modulation 1
t48c893 rev. a4, 22-jan-02 64 (82) combination mode 4: manchester modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 5: the modulator 2 of timer 2 modulates the ssi data output to manchester code the 4 bit stage can be used as prescaler for the ssi to generate the stop signal for modulator 2. the ssi has a special mode to supply the prescaler with the shiftclock. the control output signal (omsk) of the ssi is used as stop signal for the modulator. this is an example for a 12-bit manchester telegram: 00000000 1234012 0 counter 2/1 = compare register 2/1 (= 4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scli buffer full sir so sc msm timer 2 mode 3 scl counter 2/1 omsk t2o 13837 3 figure 72. manchester modulation 2 combination mode 5: biphase modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 4: the modulator 2 of timer 2 modulates the ssi data output to biphase code the 4-bit stage can be used as prescaler for the ssi to generate the stop signal for modulator 2. the ssi has a special mode to supply the prescaler via the shift-clock. the control output signal (omsk) of the ssi is used as stop signal for the modulator. this is an example for a 13-bit biphase telegram: 00000000 12345 0 counter 2/1 = compare register 2/1 (= 5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scli buffer full sir so sc msm timer 2 mode 3 scl counter 2/1 omsk t2o 13838 012 figure 73. biphase modulation
t48c893 t48c893 rev. a4, 22-jan-02 65 (82) combination mode timer 3 and ssi 8 ? bit counter 3 res compare 3/1 t3co1 t3cp t3co2 timer 3 ? control t3o cl3 t3i t3ex syscl t1out pout i/o ? bus compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu ? lator 3 m2 control so tog3 int5 res cm31 t3i t3ex si sc t3m t3cs cp3 13877 8 ? bit shift register msb lsb shift_cl so sic1 sic2 sisc scli control stb srb si output int3 i/o ? bus ssi ? control tog2 pout t1out syscl si mcl_sc mcl_sd transmit buffer receive buffer sc sc si figure 74. combination timer 3 and ssi combination mode 6: fsk modulation ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 3 mode 8: fsk modulation with shift register data (so) the two compare registers are used to generarte two varied time intervals. the ssi data output selects which compare register is used for the output frequency generation. a ? 0 ? -level at the ssi data output enables the compare register 1 and a ? 1 ? -level enables the compare register 2. the both compare and compare mode registers must be programmed to generate the two frequencies via the output toggle flip-flop. the ssi can be supplied with the toggle signal of t imer 2 or any other clock source. the timer 3 counter is driven by an internal or external clock source. 01234012340120 counter 3 cm31 cm32 so 13893 120120120120120120120 12340 t3r 12 t3o 3 01 0 40 figure 75. fsk modulation
t48c893 rev. a4, 22-jan-02 66 (82) combination mode 7: pulse width modulation (pwm) ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 3 mode 9: pulse width modulation with the shift register data (so) the two compare registers are used to generarte two varied time intervals. the ssi data output selects which compare register is used for the output pulse generation. in this mode both compare and compare mode registers must be pro- grammed to generate the two pulse width. it is also useful to enable the single action mode for extreme duty cycles. timer 2 is used as baudrate generator and for the triggered restart of timer 3. the ssi must be supplied with the toggle signal of timer 2. the counter is driven by an internal or external clock source. 000000000 0000 counter 3 cm31 cm32 t3o 13816 000001234567891011121314150 12345 tog2 67 8 1 911 12 10 14 13 0 2 3 14 15 0 0 01 sir so sco t3r figure 76. pulse-width modulation combination mode 8: manchester demodulation / pulse width demodulation ssi mode 1: 8-bit shift register internal data input (si) and the internal shift clock (sci) from the timer 3 timer 3 mode 10: manchester demodulation / pulse width demodulation with timer 3 for manchester demodulation the edge detection stage must be programmed to detect each edge at the input. these edges are evaluated by the demodulator stage. the timer stage is used to generate the shift clock for the ssi. a compare register 1 match event defines the correct moment for shifting the state from the input t3i as the decoded bit into shift register. after that the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. the compare register 2 can be used to detect a time error and handle it with an interrupt routine. before activating the demodulator mode the timer and the demodulator stage must be synchronized with the bitstream. the manchester code timing consists of parts with the half bitlength and the complete bitlength. a synchronization routine must start the demodulator after an interval with the complete bitlength. the counter can be driven by any internal clock source. the output t3o can be used by timer 2 in this mode. the manchester decoder can also be used for pulse-width demodulation. the input must programmed to detect the positive edge. the demodulator and timer must be synchronized with the leading edge of the pulse. after that a counter match with the compare register 1 shifts the state at the input t3i into the shift register. the next positive edge at the input restarts the timer.
t48c893 t48c893 rev. a4, 22-jan-02 67 (82) 1011100 110 11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 synchronize manchester demodulation mode timer 3 mode t3ex si sr ? data 13817 t3i cm31=sci 100110 bit 0 figure 77. manchester demodulation combination mode 9: biphase demodulation ssi mode 1: 8-bit shift register internal data input (si) and the internal shift clock (sci) from the timer 3 timer 3 mode 11: biphase demodulation with timer 3 in the biphase demodulation mode the timer works like in the manchester demodulation mode. the diffenence is that the bits are decoded with the toggle flip-flop. this flip-flop samples the edge in the middle of the bitframe and the compare register 1 match event shifts the toggle flip-flop output into shift register. before activating the demodulation the timer and the demodulation stage must be synchronized with the bitstream. the biphase code timing consists of parts with the half bitlength and the complete bitlength. the synchronization routine must start the demodulator after an interval with the complete bitlength. the counter can be driven by any internal clock source and the output t3o can be used by timer 2 in this mode. 011 1 1 01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 synchronize biphase demodulation mode timer 3 mode t3ex q1=si cm31=sci sr ? data 13818 0000 t3i reset counter 3 101010 bit 0 figure 78. biphase demodulation
t48c893 rev. a4, 22-jan-02 68 (82) combination mode timer 2 and timer 3 8-bit counter 3 res compare 3/1 t3co1 t3cp t3co2 timer 3 ? control t3o cl3 t3i t3ex syscl t1out pout i/o-bus 13878 compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu ? lator 3 control so tog3 int5 res cm31 t3i t3ex tog2 si sci ssi cp3 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 cm1 pout ssi cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm tog2 int4 biphase ? , manchester ? modulator output mout m2 t2o timer 2 modulator 2 output-stage t2m2 control (re, fe, sco, omsk) ssi t2c cl2/1 tog3 syscl t1out scl timer 2 ? control m2 t3cs t3m pout dcgo so t2i i/o-bus i/o-bus figure 79. combination timer 3 and timer 2
t48c893 t48c893 rev. a4, 22-jan-02 69 (82) combination mode 10: frequency measurement or event counter with time gate timer 2 mode 1/2: 12-bit compare counter / 8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 compare match toggles (tog2) to the timer 3 timer 3 mode 3: timer / counter; int. trigger restart & int. capture (with timer 2 tog2 ? signal) the counter is driven by an external (t3i) clock source. the output signal (tog2) of timer 2 resets the counter. the counter value before reset is saved in the capture register. if single-action mode is activated for one or both compare registers, the trigger signal restarts also the single actions. this mode can be used for frequency measurements or as event counter with time gate. 0012345678910 counter 3 tog2 t3cp ? register 13879 t3i t3r capture value = 0 capture value = 17 capture value = 18 11121314151617 123456789101112131415161718 0 0123 45 figure 80. frequency measurements 0012345678910 counter 3 tog2 t3cp ? register 13814 11 0 1 2 401 t3i 2 3 t3r capture value = 0 capture value = 11 capture value = 4 figure 81. event counter with time gate combination mode 11: burst modulation 1 timer 2 mode 1/2: 12-bit compare counter / 8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 compare match toggles the output flip-flop (m2) to the timer 3 timer 3 mode 6: carrier frequency burst modulation controlled by timer 2 output (m2) the timer 3 counter is driven by an internal or external clock source. its compare- and compare mode registers must be programmed to generate the carrier frequency with the output toggle flip-flop. the output toggle flip-flop (m2) of timer 2 is used to enable and disable the timer 3 output. the timer 2 can be driven by the toggle output signal of timer 3 (tog3) or any other clock source. 0101234501012345010123450101 50101 50101 50101 50101 50101 50101 50101 50101 50101 30 1 2 3 3 0 1 3 2 cl3 counter 3 cm1 cm2 tog3 m3 counter 2/2 tog2 m2 t3o 13880 figure 82. burst modulation 1
t48c893 rev. a4, 22-jan-02 70 (82) combination mode timer 2, timer 3 and ssi 8 ? bit counter 3 res compare 3/1 t3co1 t3cp t3co2 timer 3 ? control t3o cl3 t3i t3ex syscl t1out pout i/o ? bus compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu ? lator 3 control so tog3 int5 res cm31 t3i t3ex tog2 si sci ssi cp3 4 ? bit counter 2/1 res ovf1 compare 2/1 t2co1 cm1 pout cl2/2 dcg t2m1 p4cr 8 ? bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm tog2 int4 biphase ? , manchester ? modulator output mout m2 t2o timer 2 modulator 2 output ? stage t2m2 control (re, fe, sco, omsk) t2c cl2/1 tog3 syscl t1out scl timer 2 ? control m2 t3cs t3m pout dcgo so t2i i/o ? bus i/o ? bus 13881 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc scli control stb srb si output int3 i/o ? bus ssi ? control tog2 pout t1out syscl mcl_sc mcl_sd transmit buffer receive buffer sc si scl figure 83. combination timer 2, timer 3 and ssi
t48c893 t48c893 rev. a4, 22-jan-02 71 (82) combination mode 12: burst modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 2 output mode 2: 8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 compare match toggles (tog2) to the ssi timer 3 mode 7: carrier frequency burst modulation controlled by the internal output (so) of ssi the timer 3 counter is driven by an internal or external clock source. its compare- and compare mode registers must be programmed to generate the carrier frequency with the output toggle flip-flop (m3). the internal data output (so) of the ssi is used to enable and disable the timer 3 output. the ssi can by supplied with the toggle signal of timer 2. 0101234501012345010123450101 50101 50101 50101 50101 50101 50101 50101 50101 50101 30 1 2 3 3 0 1 3 2 cl3 counter 3 cm31 cm32 tog3 m3 counter 2/2 tog2 so t3o 13882 figure 84. burst modulation 2 combination mode 13: fsk modulation ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 2 output mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 4-bit compare match signal (pout) to the ssi timer 3 mode 8: fsk modulation with shift register data output (so) the two compare registers are used to generate two different time intervals. the ssi data output selects which compare register is used for the output frequency generation. a ? 0 ? level at the ssi data output enables the compare register 1 and an ? 1 ? level enables the compare register 2. the both compare- and compare mode registers must be programmed to generate the two frequencies via the output toggle flip-flop. the ssi can be supplied with the toggle signal of t imer 2 or any other clock source. the timer 3 counter is driven by an internal or external clock source. 01234012340123 counter 3 cm31 cm32 so 13815 401201201201201201201 20123 t3r 40 t3o 1 01 0 figure 85. fsk modulation
t48c893 rev. a4, 22-jan-02 72 (82) 5 data eeprom the internal data eeprom offers two pages of 512 bit each. both pages are organized as 32 16 bit words. the programming vo ltage as well as write cycle timing is gen- erated on chip. to be compatible with the rom parts m44cx90/x92 two restrictions have to be taken into ac- count: to use the same eeprom page as with the rom parts the application software has to write the i 2 c-com- mand ? 09h ? to the eeprom. this command has no effect for the m44cx90/x92 if it is left inside the hex-file for the rom version. data handling for read and write is performed using the serial interface mcl. the page select is performed by either writing ? 01h ? (page 1) or ? 09h ? (page 0) to the eeprom 16 ? bit read/write buffer address control 8 ? bit data register eeprom 2 32 16 hv ? generator timing control mode control i/o control scl v dd v ss sda page 1 page 0 ?? > write ? 01h ? ?? > write ? 09h ? figure 86. block diagram eeprom
t48c893 t48c893 rev. a4, 22-jan-02 73 (82) 5.1 serial interface the eeprom uses an i 2 c-like two-wire serial interface to the microcontroller for read and write accesses to the data. it is considered to be a slave in all these applications. that means, the controller has to be the master that initiates the data transfer and provides the clock for transmit and receive operations. the serial interface is controlled by the microcontroller which generates the serial clock and controls the access via the scl-line and sda-line. scl is used to clock the data into and out of the device. sda is a bidirectional line that is used to transfer data into and out of the device. the following protocol is used for the data transfers. serial protocol data states on the sda-line changing only while scl is low. changes on the sda-line while scl is high are interpreted as start or stop condition. a start condition is defined as high to low transi- tion on the sda-line while the scl-line is high. a stop condition is defined as low to high transition on the sda-line while the scl-line is high. each data transfer must be initialized with a start condition and terminated with a stop condition. the start condition wakes the device from standby mode and the stop condition returns the device to standby mode. a receiving device generates an acknowledge (a) after the reception of each byte. this requires an additional clock pulse, generated by the master. if the reception was successful the receiving master or slave device pulls down the sda-line during that clock cycle. if an acknowledge is not detected (n) by the interface in transmit mode, it will terminate further data transmissions and go into receive mode. a master device must finish its read operation by a non-ac- knowledge and then send a stop condition to bring the device into a known state. start condition data valid data change data/ acknowledge valid stop condition 13884 scl sda stand by stand- by figure 87. i 2 c protocol before the start condition and after the stop condition the device is in stand-by mode and the sda line is switched as input with pull-up resistor. the control byte that follows the start condition de- termines the following operation. it consists of the 5-bit row address, 2 mode control bits and the read / nwrite bit that is used to control the direction of the following transfer. a ? 0 ? defines a write access and a ? 1 ? a read access. control byte format: eeprom address mode control bits read/ nwrite start a4 a3 a2 a1 a0 c1 c0 r/nw ackn control byte format: start control byte ackn data byte ackn data byte ackn stop
t48c893 rev. a4, 22-jan-02 74 (82) 5.1.1 eeprom the eeprom has a size of 2 512 bits and is organized as 32 x 16-bit matrix each. to read and write data to and from the eeprom the serial interface must be used. the interface supports one and two byte write accesses and one to n-byte read accesses to the eeprom. eeprom ? operating modes the operating modes of the eeprom are defined via the control byte. the control byte contains the row address, the mode control bits and the read/not-write bit that is used to control the direction of the following transfer. a ? 0 ? defines a write access and a ? 1 ? a read access. the five address bits select one of the 32 rows of the eeprom memory to be accessed. for all accesses the complete 16-bit word of the selected row is loaded into a buffer. the buffer must be read or overwritten via the serial interface. the two mode control bits c1 and c2 define in which or- der the accesses to the buffer are performed: high byte ? low byte or low byte ? high byte. the eeprom also sup- ports autoincrement and autodecrement read operations. after sending the start address with the corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses. two special control bytes enable the complete initialization of eeprom with ? 0 ? or with ? 1. write operations the eeprom permits 8-bit and 16-bit write operations. a write access starts with the start condition followed by a write control byte and one or two data bytes from the master. it is completed via the stop condition from the master after the acknowledge cycle. the programming cycle consists of an erase cycle (write ? zeros ? ) and the write cycle (write ? ones ? ). both cycles together take about 10 ms. acknowledge polling if the eeprom is busy with an internal write cycle, all inputs are disabled and the eeprom will not acknowledge until the write cycle is finished. this can be used to detect the end of the write cycle. the master must perform acknowledge polling by sending a st art condition followed by the control byte. if the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform fur- ther acknowledge polling sequences. if the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. write one data byte start control byte a data byte 1 a stop write two data bytes start control byte a data byte 1 a data byte 2 a stop write control byte only start control byte a stop write control bytes msb lsb write low byte first a4 a3 a2 a1 a0 c1 c0 r/nw row address 0 1 0 byte order lb(r) hb(r) msb lsb write high byte first a4 a3 a2 a1 a0 c1 c0 r/nw row address 1 0 0 byte order hb(r) lb(r) a ? > acknowledge; hb: high byte; lb: low byte; r: row address
t48c893 t48c893 rev. a4, 22-jan-02 75 (82) read operations the eeprom allows byte-, word- and current address read operations. the read operations are initiated in the same way as write operations. every read access is initi- ated by sending the start condition followed by the control byte which contains the address and the read mode. after the device receives a read command it re- turns an acknowledge, loads the addressed word into the read\write buffer and sends the selected data byte to the master. the master has to acknowledge the received byte if it wants to proceed the read operation. if two bytes are read out from the buffer the device increments respec- tively decrements the word address automatically and loads the buffer with the next word. the read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decre- mented for the next read access. if the memory address limit is reached, the data word address will ? roll over ? and the sequential read will continue. the master can termi- nate the read operation after every byte by not responding with an acknowledge (n) and by issuing a stop condition. read one data byte start control byte a data byte 1 n stop read two data bytes start control byte a data byte 1 a data byte 2 n stop read n data bytes start control byte a data byte 1 a data byte 2 a ? ? ? ? data byte n n stop read control bytes msb lsb read low byte first, address increment a4 a3 a2 a1 a0 c1 c0 r/nw row address 0 1 1 byte order lb(r) hb(r) lb(r+1) hb(r+1) ? ? ? lb(r+n) hb(r+n) msb lsb read high byte first, addr. decrement a4 a3 a2 a1 a0 c1 c0 r/nw row address 1 0 1 byte order hb(r) lb(r) hb(r ? 1) lb(r ? 1) ? ? ? hb(r ? n) lb(r ? n) a ? > acknowledge, n ? > no acknowledge; hb: high byte; lb: low byte, r: row address initialization the serial interface to the eeprom to prevent unexpected behaviour of the eeprom and its interface it is good practice to use an initialization sequence after any reset of the circuit. this is performed by writing: start ? ffh ? a n stop to the serial interface. if the eeprom acknowledges this sequence it is in a defined state. maybe it is necessary to perform this sequence twice.
t48c893 rev. a4, 22-jan-02 76 (82) 6 electrical characteristics 6.1 absolute maximum ratings voltages are given relative to v ss parameters symbol value unit supply voltage v dd ? 0.3 to + 6.5 v input voltage (on any pin) v in v ss ? 0.3 v in v dd +0.3 v output short circuit duration t short indefinite s operating temperature range t amb ? 40 to +85 c storage temperature range t stg ? 40 to +130 c thermal resistance (sso20) r thja 140 k/w soldering temperature (t 10 s) t sld 260 c stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating condition for an extended period may affect device reliability. all inputs and outputs are protected against high electrostatic voltages or electric fields. however, precautions to minimize the build-up of electrostatic charges during handling are recommended. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. v dd ). 6.2 dc operating characteristics v ss = 0 v, t amb = ? 40 to 85 c unless otherwise specified. parameters test conditions / pins symbol min. typ. max. unit power supply operating voltage at v dd v dd v por 6.5 v active current cpu active f syscl = 1 mhz v dd = 1.8 v v dd = 3.0 v v dd = 6.5 v i dd 0.2 0.3 0.7 0.4 1.0 ma ma ma power down current (cpu sleep, rc oscillator active, 4-mhz quartz-osc. active) f syscl = 1 mhz v dd = 1.8 v v dd = 3.0 v v dd = 6.5 v i pd 40 70 200 150 a a a sleep current (cpu sleep, 32-khz quartz-osc. active 4-mhz quartz-osc. inactive) v dd = 1.8 v v dd = 3.0 v v dd = 6.5 v i sleep 0.4 0.6 0.8 1.5 2.0 a a a sleep current (cpu sleep, 32-khz quartz-osc. inactive 4-mhz quartz-osc. inactive) v dd = 3.0 v v dd = 6.5 v i sleep 0.3 0.6 1.0 1.8 a a pin capacitance any pin to v ss c l 7 10 pf
t48c893 t48c893 rev. a4, 22-jan-02 77 (82) v ss = 0 v, t amb = ? 40 to 85 c unless otherwise specified. parameters test conditions / pins symbol min. typ. max. unit power-on reset threshold voltage por threshold voltage bot = 1 v por 1.54 1.7 1.88 v por threshold voltage bot = 0 v por 1.83 2.0 2.20 v por hysteresis v por 50 mv voltage monitor threshold voltage vm high threshold voltage v dd > vm, vms = 1 v mthh 3.0 3.35 v vm high threshold voltage v dd < vm, vms = 0 v mthh 2.77 3.0 v vm middle thresh. voltage v dd > vm, vms = 1 v mthm 2.6 2.9 v vm middle thresh. voltage v dd < vm, vms = 0 v mthm 2.4 2.6 v vm low threshold voltage v dd > vm, vms = 1 v mthl 2.2 2.44 v vm low threshold voltage v dd < vm, vms = 0 v mthl 2.0 2.2 v external input voltage vmi v dd = 3 v, vms = 1 v vmi 1.3 1.4 v vmi v dd = 3 v, vms = 0 v vmi 1.18 1.3 v all bidirectional ports v ss = 0 v, t amb = ? 40 to 85 c unless otherwise specified. parameters test conditions / pins symbol min. typ. max. unit input voltage low v dd = 1.8 to 6.5 v v il v ss 0.2*v dd v input voltage high v dd = 1.8 to 6.5 v v ih 0.8* v dd v dd v input low current (switched pull-up) v dd = 2.0 v, v dd = 3.0 v, v il = v ss v dd = 6.5 v i il ? 3 ? 10 ? 80 ? 8 ? 20 ? 150 ? 14 ? 40 ? 240 a a a input high current (switched pull-down) v dd = 2.0 v, v dd = 3.0 v, v ih = v dd v dd = 6.5 v i ih 3 10 60 6 20 100 14 40 160 a a a input low current (static pull-up) v dd = 2.0 v v dd = 3.0 v, v il = v ss v dd = 6.5 v i il ? 30 ? 80 ? 300 ? 50 ? 160 ? 700 ? 90 ? 320 ? 1200 a a a input low current (static pull-down) v dd = 2.0 v v dd = 3.0 v, v ih = v dd v dd = 6.5 v i ih 20 80 300 50 160 600 100 320 1000 a a a input leakage current v il = v ss i il 100 na input leakage current v ih = v dd i ih 100 na output low current v ol = 0.2 v dd v dd = 2.0 v v dd = 3.0 v, v dd = 6.5 v i ol 0.9 3 8 1.8 5 15 3.6 8 22 ma ma ma output high current v oh = 0.8 v dd v dd = 2.0 v v dd = 3.0 v, v dd = 6.5 v i oh ? 0.8 ? 3 ? 8 ? 1.7 ? 5 ? 15 ? 3.4 ? 8 ? 24 ma ma ma note: the pin bp20/nte has a static pull-up resistor during the reset-phase of the microcontroller
t48c893 rev. a4, 22-jan-02 78 (82) 6.3 ac characteristics operation cycle time (v ss = 0 v) parameters test conditions / pins symbol min. typ. max. unit system clock cycle v dd = 1.8 to 6.5 v t amb = ? 40 to 85 c t syscl 500 2000 ns v dd = 2.4 to 6.5 v t amb = ? 40 to 85 c t syscl 250 2000 ns supply voltage v dd = 1.8 to 6.5 v, v ss = 0 v, t amb = 25 c unless otherwise specified. parameters test conditions / pins symbol min. typ. max. unit timer 2 input timing pin t2i timer 2 input clock f t2i 5 mhz timer 2 input low time rise / fall time < 10 ns t t2il 100 ns timer 2 input high time rise / fall time < 10 ns t t2ih 100 ns timer 3 input timing pin t3i timer 3 input clock f t3i syscl/2 mhz timer 3 input low time rise / fall time < 10 ns t t3il 2 t syscl ns timer 3 input high time rise / fall time < 10 ns t t3ih 2 t syscl ns interrupt request input timing int. request low time rise / fall time < 10 ns t irl 100 ns int. request high time rise / fall time < 10 ns t irh 100 ns external system clock exscl at osc1, ecm = en rise / fall time < 10 ns f exscl 0.5 4 mhz exscl at osc1, ecm = di rise / fall time < 10 ns f exscl 0.02 4 mhz input high time rise / fall time < 10 ns t ih 0.1 s reset timing power-on reset time v dd v por t por 1.5 5 ms rc oscillator 1 frequency f rcout1 4.0 mhz stability v dd = 2.0 to 6.5 v t amb = ? 40 to 85 c ? f/f 50 % rc oscillator 2 ? external resistor frequency r ext = 180 k ? f rcout2 4.0 mhz stability v dd = 2.0 to 6.5 v t amb = ? 40 to 85 c ? f/f 15 % stabilization time t s 10 s 4-mhz crystal oscillator (operating range v dd = 2.2 v to 6.5 v) frequency f x 4 mhz start-up time t sq 5 ms stability ? f/f ? 10 10 ppm integrated input / output capacitances (configurable) c in / c out programmable c in c out 0, 2, 5, 7, 10 or 12 0, 2, 5, 7, 10 or 12 pf pf
t48c893 t48c893 rev. a4, 22-jan-02 79 (82) unit max. typ. min. symbol test conditions / pins parameters 32-khz crystal oscillator (operating range v dd = 2.0 v to 6.5 v) frequency f x 32.768 khz start-up time t sq 0.5 s stability ? f/f ? 10 10 ppm integrated input / output capacitances (mask programmable) c in / c out programmable c in c out 0, 2, 5, 7, 10 or 12 0, 2, 5, 7, 10 or 12 pf pf external 32-khz crystal parameters crystal frequency f x 32.768 khz serial resistance rs 30 50 k ? static capacitance c 0 1.5 pf dynamic capacitance c1 3 ff external 4-mhz crystal parameters crystal frequency f x 4.0 mhz serial resistance rs 40 150 ? static capacitance c 0 1.4 3 pf dynamic capacitance c1 3 ff crystal characteristics l c1 rs c0 oscin oscout equivalent circuit 96 11553 sclin sclout figure 88. crystal equivalent circuit supply voltage v dd = 1.8 to 6.5 v, v ss = 0 v, t amb = 25 c unless otherwise specified. parameters test conditions / pins symbol min. typ. max. unit data eeprom operating current during erase/write cycle i wr 600 1300 a endurance erase- / write-cycles t amb = 85 c n ew n ew 500,000 100,000 1,000,000 cycles cycles data erase/write cycle time for 16-bit access t dew 9 13 ms data retention time t amb = 85 c t dr t dr 100 10 years years power-up to read operation t pur 0.2 ms power-up to write opera- tion t puw 0.2 ms program eeprom erase- / write-cycles t amb = 0 to 40 c n ew 100 1,000 cycles serial interface scl clock frequency f sc_mcl 100 500 khz
t48c893 rev. a4, 22-jan-02 80 (82) 7 package information 13007 technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 110
t48c893 t48c893 rev. a4, 22-jan-02 81 (82) 8 selectable options port 1 bp10 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp13 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong port 2 bp20 cmos pull-up open drain [n] pull-down pull-up strong bp21 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp22 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp23 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong port 4 bp40 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp41 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp42 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp43 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong port 5 bp50 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp51 cmos pull-up open drain [n] pull-down ] pull-up strong pull-down strong bp52 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp53 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong port 6 bp60 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong bp63 cmos pull-up open drain [n] pull-down pull-up strong pull-down strong osc1 no integrated capacitance internal capacitance ( ___ pf) osc2 no integrated capacitance internal capacitance ( ___ pf) clock used external resistor external clock 32-khz crystal 4-mhz crystal ecm ( external clock monitor) enable disable
t48c893 rev. a4, 22-jan-02 82 (82) ozone depleting substances policy statement it is the policy of atmel germany gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. atmel germany gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. atmel germany gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 12. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use atmel products for any unintended or unauthorized application, the buyer shall indemnify atmel against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. data sheets can also be retrieved from the internet: http://www.atmel ? wm.com atmel germany gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2594, fax number: 49 (0)7131 67 2423

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